Merge branch 'drm-intel-fixes' into drm-intel-next

Apply the trivial conflicting regression fixes, but keep GPU semaphores
enabled.

Conflicts:
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/i915/i915_gem_execbuffer.c

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
index d659f36419af48a92e3dde13dd0dbbd553e0df71,4ff9b6cc973f031f363b8a25c669765793920951..09e0327fc6cee13288ba6950eb3cf765f6be1146
--- 1/drivers/gpu/drm/i915/i915_debugfs.c
--- 2/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@@ -873,18 -865,10 +873,18 @@@ static int i915_cur_delayinfo(struct se
                int max_freq;
  
                /* RPSTAT1 is in the GT power well */
-               __gen6_force_wake_get(dev_priv);
+               __gen6_gt_force_wake_get(dev_priv);
  
 +              rpstat = I915_READ(GEN6_RPSTAT1);
 +              rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 +              rpcurup = I915_READ(GEN6_RP_CUR_UP);
 +              rpprevup = I915_READ(GEN6_RP_PREV_UP);
 +              rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 +              rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 +              rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 +
                seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 -              seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
 +              seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
                seq_printf(m, "Render p-state ratio: %d\n",
                           (gt_perf_status & 0xff00) >> 8);
                seq_printf(m, "Render p-state VID: %d\n",

diff --cc drivers/gpu/drm/i915/i915_drv.c
index bdf4ceb1049df11e01e6908c3c697e309b21433b,22ec066adae68ffd83432b37e149e8344c65d744..3dba19f28e44f242b474992287463bc4bf57295a
--- 1/drivers/gpu/drm/i915/i915_drv.c
--- 2/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@@ -49,6 -46,9 +49,9 @@@ module_param_named(panel_ignore_lid, i9
  unsigned int i915_powersave = 1;
  module_param_named(powersave, i915_powersave, int, 0600);
  
 -unsigned int i915_semaphores = 0;
++unsigned int i915_semaphores = 1;
+ module_param_named(semaphores, i915_semaphores, int, 0600);
+ 
  unsigned int i915_enable_rc6 = 0;
  module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  

diff --cc drivers/gpu/drm/i915/i915_drv.h
index 9f3650c9882a2b674e0bc7f2b7a766d1d2ef6d4f,456f4048483827d04c84375e0268351057688d15..b68abf19bce88b4dbeae69d21ccbef9ec4404a90
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -959,11 -955,10 +959,12 @@@ enum intel_chip_family 
  extern struct drm_ioctl_desc i915_ioctls[];
  extern int i915_max_ioctl;
  extern unsigned int i915_fbpercrtc;
 +extern int i915_panel_ignore_lid;
  extern unsigned int i915_powersave;
+ extern unsigned int i915_semaphores;
  extern unsigned int i915_lvds_downclock;
  extern unsigned int i915_panel_use_ssc;
 +extern int i915_vbt_sdvo_panel_type;
  extern unsigned int i915_enable_rc6;
  
  extern int i915_suspend(struct drm_device *dev, pm_message_t state);
@@@ -1364,4 -1375,54 +1370,11 @@@ static inline u32 i915_gt_read(struct d
        return val;
  }
  
 -
 -static inline void
 -i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
 -{
 -       /* Trace down the write operation before the real write */
 -       trace_i915_reg_rw('W', reg, val, len);
 -       switch (len) {
 -       case 8:
 -               writeq(val, dev_priv->regs + reg);
 -               break;
 -       case 4:
 -               writel(val, dev_priv->regs + reg);
 -               break;
 -       case 2:
 -               writew(val, dev_priv->regs + reg);
 -               break;
 -       case 1:
 -               writeb(val, dev_priv->regs + reg);
 -               break;
 -       }
 -}
 -
 -/**
 - * Reads a dword out of the status page, which is written to from the command
 - * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 - * MI_STORE_DATA_IMM.
 - *
 - * The following dwords have a reserved meaning:
 - * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 - * 0x04: ring 0 head pointer
 - * 0x05: ring 1 head pointer (915-class)
 - * 0x06: ring 2 head pointer (915-class)
 - * 0x10-0x1b: Context status DWords (GM45)
 - * 0x1f: Last written status offset. (GM45)
 - *
 - * The area from dword 0x20 to 0x3ff is available for driver usage.
 - */
 -#define READ_HWSP(dev_priv, reg)  (((volatile u32 *)\
 -                      (LP_RING(dev_priv)->status_page.page_addr))[reg])
 -#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 -#define I915_GEM_HWS_INDEX            0x20
 -#define I915_BREADCRUMB_INDEX         0x21
 -
+ static inline void i915_gt_write(struct drm_i915_private *dev_priv,
+                               u32 reg, u32 val)
+ {
+       if (dev_priv->info->gen >= 6)
+               __gen6_gt_wait_for_fifo(dev_priv);
+       I915_WRITE(reg, val);
+ }
  #endif

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 8513c04dc892f71555d8601a1b5b92272eae8821,50ab1614571c746447781758c8355cb251276019..7ff7f933ddf17e1395ab7140be773bda10a7132b
--- 1/drivers/gpu/drm/i915/i915_gem_execbuffer.c
--- 2/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@@ -748,8 -772,9 +748,9 @@@ i915_gem_execbuffer_sync_rings(struct d
        if (from == NULL || to == from)
                return 0;
  
-       if (INTEL_INFO(obj->base.dev)->gen < 6)
+       /* XXX gpu semaphores are implicated in various hard hangs on SNB */
+       if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
 -              return i915_gem_object_wait_rendering(obj, true);
 +              return i915_gem_object_wait_rendering(obj);
  
        idx = intel_ring_sync_index(from, to);
  

diff --cc drivers/gpu/drm/i915/i915_gem_tiling.c
index 1f45019e6da39b2e514be499805c1313f6203bc1,d64843e18df2c6d0565801c44ea96353b780c2d3..281ad3d6115d08a3f40a666b60673b0d22cd6d6e
--- 1/drivers/gpu/drm/i915/i915_gem_tiling.c
--- 2/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@@ -298,9 -284,14 +284,10 @@@ i915_gem_set_tiling(struct drm_device *
        struct drm_i915_gem_set_tiling *args = data;
        drm_i915_private_t *dev_priv = dev->dev_private;
        struct drm_i915_gem_object *obj;
 -      int ret;
 -
 -      ret = i915_gem_check_is_wedged(dev);
 -      if (ret)
 -              return ret;
++      int ret = 0;
  
        obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 -      if (obj == NULL)
 +      if (&obj->base == NULL)
                return -ENOENT;
  
        if (!i915_tiling_ok(dev,

diff --cc drivers/gpu/drm/i915/i915_reg.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ringbuffer.h
Simple merge