KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bits

Allow a guest hypervisor to trap accesses to CNT{P,V}CT_EL02 by
propagating these trap bits to the host trap configuration.

Acked-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20241217142321.763801-10-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c
index 6f04f31c0a7f22b21114193d62741352ac02e1f6..e5951e6eaf2360867518cc68a61895b48931eeca 100644 (file)
--- a/arch/arm64/kvm/arch_timer.c
+++ b/arch/arm64/kvm/arch_timer.c
@@ -824,6 +824,10 @@ static void timer_set_traps(struct kvm_vcpu *vcpu, struct timer_map *map)
         * Apply the enable bits that the guest hypervisor has requested for
         * its own guest. We can only add traps that wouldn't have been set
         * above.
+        * Implementation choices: we do not support NV when E2H=0 in the
+        * guest, and we don't support configuration where E2H is writable
+        * by the guest (either FEAT_VHE or FEAT_E2H0 is implemented, but
+        * not both). This simplifies the handling of the EL1NV* bits.
         */
        if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
                u64 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
@@ -834,6 +838,9 @@ static void timer_set_traps(struct kvm_vcpu *vcpu, struct timer_map *map)
 
                tpt |= !(val & (CNTHCTL_EL1PCEN << 10));
                tpc |= !(val & (CNTHCTL_EL1PCTEN << 10));
+
+               tpt02 |= (val & CNTHCTL_EL1NVPCT);
+               tvt02 |= (val & CNTHCTL_EL1NVVCT);
        }
 
        /*