#define SGMII_LINK_MAC_MAC_FORCED      2
 #define SGMII_LINK_MAC_FIBER           3
 #define SGMII_LINK_MAC_PHY_NO_MDIO     4
+#define RGMII_LINK_MAC_PHY             5
+#define RGMII_LINK_MAC_PHY_NO_MDIO     7
 #define XGMII_LINK_MAC_PHY             10
 #define XGMII_LINK_MAC_MAC_FORCED      11
 
 
                                     ALE_PORT_STATE_FORWARD);
 
                if (ndev && slave->open &&
-                   slave->link_interface != SGMII_LINK_MAC_PHY &&
-                   slave->link_interface != XGMII_LINK_MAC_PHY)
+                   ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
+                   (slave->link_interface != RGMII_LINK_MAC_PHY) &&
+                   (slave->link_interface != XGMII_LINK_MAC_PHY)))
                        netif_carrier_on(ndev);
        } else {
                writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
                                     ALE_PORT_STATE,
                                     ALE_PORT_STATE_DISABLE);
                if (ndev &&
-                   slave->link_interface != SGMII_LINK_MAC_PHY &&
-                   slave->link_interface != XGMII_LINK_MAC_PHY)
+                   ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
+                   (slave->link_interface != RGMII_LINK_MAC_PHY) &&
+                   (slave->link_interface != XGMII_LINK_MAC_PHY)))
                        netif_carrier_off(ndev);
        }
 
 
        slave->open = false;
        if ((slave->link_interface == SGMII_LINK_MAC_PHY) ||
+           (slave->link_interface == RGMII_LINK_MAC_PHY) ||
            (slave->link_interface == XGMII_LINK_MAC_PHY))
                slave->phy_node = of_parse_phandle(node, "phy-handle", 0);
        slave->port_num = gbe_get_slave_port(gbe_dev, slave->slave_num);
        if (slave->link_interface == SGMII_LINK_MAC_PHY) {
                phy_mode = PHY_INTERFACE_MODE_SGMII;
                slave->phy_port_t = PORT_MII;
+       } else if (slave->link_interface == RGMII_LINK_MAC_PHY) {
+               phy_mode = PHY_INTERFACE_MODE_RGMII;
+               slave->phy_port_t = PORT_MII;
        } else {
                phy_mode = PHY_INTERFACE_MODE_NA;
                slave->phy_port_t = PORT_FIBRE;
 
        for_each_sec_slave(slave, gbe_dev) {
                if ((slave->link_interface != SGMII_LINK_MAC_PHY) &&
+                   (slave->link_interface != RGMII_LINK_MAC_PHY) &&
                    (slave->link_interface != XGMII_LINK_MAC_PHY))
                        continue;
                slave->phy =