clk: qcom: rpmh: Add support for SM8550 rpmh clocks

Adds the RPMH clocks present in SM8550 SoC.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104093450.3150578-4-abel.vesa@linaro.org

diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 586a810c682cac7c40532cde8e0af032973576a5..7db5a53d73f022f118fca73337f843ba8c732d32 100644 (file)
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -366,6 +366,16 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
 DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
 DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
 
+DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
+DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
+DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
+DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
+DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
+
+DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
+DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2);
+DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2);
+
 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
 
 DEFINE_CLK_RPMH_BCM(ce, "CE0");
@@ -576,6 +586,31 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
        .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks),
 };
 
+static struct clk_hw *sm8550_rpmh_clocks[] = {
+       [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
+       [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
+       [RPMH_LN_BB_CLK1]       = &clk_rpmh_clk6_a2.hw,
+       [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_clk6_a2_ao.hw,
+       [RPMH_LN_BB_CLK2]       = &clk_rpmh_clk7_a2.hw,
+       [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_clk7_a2_ao.hw,
+       [RPMH_LN_BB_CLK3]       = &clk_rpmh_clk8_a2.hw,
+       [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_clk8_a2_ao.hw,
+       [RPMH_RF_CLK1]          = &clk_rpmh_clk1_a1.hw,
+       [RPMH_RF_CLK1_A]        = &clk_rpmh_clk1_a1_ao.hw,
+       [RPMH_RF_CLK2]          = &clk_rpmh_clk2_a1.hw,
+       [RPMH_RF_CLK2_A]        = &clk_rpmh_clk2_a1_ao.hw,
+       [RPMH_RF_CLK3]          = &clk_rpmh_clk3_a1.hw,
+       [RPMH_RF_CLK3_A]        = &clk_rpmh_clk3_a1_ao.hw,
+       [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a1.hw,
+       [RPMH_RF_CLK4_A]        = &clk_rpmh_clk4_a1_ao.hw,
+       [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
+       .clks = sm8550_rpmh_clocks,
+       .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
+};
+
 static struct clk_hw *sc7280_rpmh_clocks[] = {
        [RPMH_CXO_CLK]      = &clk_rpmh_bi_tcxo_div4.hw,
        [RPMH_CXO_CLK_A]    = &clk_rpmh_bi_tcxo_div4_ao.hw,
@@ -742,6 +777,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
        { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
        { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
        { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
+       { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
        { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
        { }
 };