]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
drm/amdgpu: define ras_reset_error_count function
authorTao Zhou <tao.zhou1@amd.com>
Wed, 11 Oct 2023 10:36:15 +0000 (18:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 20 Oct 2023 19:11:26 +0000 (15:11 -0400)
Make the code architecture more simple.

v2: reuse ras_reset_error_count in ras_reset_error_status.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

index c7f8dcb3b4d2d3d7d84fd4274748e74f0598a72c..a4384f0eb8bfb033535a2e91ecab222ffd8ca4f4 100644 (file)
@@ -1170,23 +1170,34 @@ out_fini_err_data:
        return ret;
 }
 
-int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
+int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
                enum amdgpu_ras_block block)
 {
        struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
 
        if (!block_obj || !block_obj->hw_ops) {
                dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
-                            ras_block_str(block));
-               return 0;
+                               ras_block_str(block));
+               return -EOPNOTSUPP;
        }
 
        if (!amdgpu_ras_is_supported(adev, block))
-               return 0;
+               return -EOPNOTSUPP;
 
        if (block_obj->hw_ops->reset_ras_error_count)
                block_obj->hw_ops->reset_ras_error_count(adev);
 
+       return 0;
+}
+
+int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
+               enum amdgpu_ras_block block)
+{
+       struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
+
+       if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
+               return 0;
+
        if ((block == AMDGPU_RAS_BLOCK__GFX) ||
            (block == AMDGPU_RAS_BLOCK__MMHUB)) {
                if (block_obj->hw_ops->reset_ras_error_status)
index 0a5c8a107fb210f19be3dd61a0333bde3e64a8e0..3f9ac0ab67e672cfbda9a159bb1c1a5fc4ea5408 100644 (file)
@@ -714,6 +714,8 @@ void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
                struct ras_query_if *info);
 
+int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
+               enum amdgpu_ras_block block);
 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
                enum amdgpu_ras_block block);