rasdaemon: cxl: Update memory module event to CXL spec rev 3.1

CXL spec 3.1 section 8.2.9.2.1.3 Table 8-47, Memory Module Event Record
has updated with following new fields and new info for Device Event Type
and Device Health Information fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type

Update the parsing, logging and recording of memory module event for the
above spec rev 3.1 changes.

Example rasdaemon log for CXL memory module event,

cxl_memory_module 2024-11-19 18:43:15 +0000 memdev:mem3 host:0000:0f:00.0 \
serial:0x3 log type:Fatal hdr_uuid:fe927475-dd59-4339-a586-79bab113b774 \
hdr_handle:0x2 hdr_related_handle:0x0 hdr_timestamp:1970-01-01 00:09:36 +0000 \
hdr_length:128 hdr_maint_op_class:0 hdr_maint_op_sub_class:1 \
event_type:Temperature Change event_sub_type:Unsupported Config Data \
health_status:'MAINTENANCE_NEEDED' 'REPLACEMENT_NEEDED' \
media_status:All Data Loss in Event of Power Loss as_life_used:Unknown \
as_dev_temp:Normal as_cor_vol_err_cnt:Normal as_cor_per_err_cnt:Normal \
life_used:8 device_temp:3 dirty_shutdown_cnt:33 cor_vol_err_cnt:25 \
cor_per_err_cnt:45 comp_id:02 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags:'Resource ID' Resource ID:fc d2 7e 2f

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/ras-cxl-handler.c b/ras-cxl-handler.c
index 9139888483207ae90bb5453184093266b574dd1f..6e5ddea6246e19857581f70e4a48aefda0f60701 100644 (file)
--- a/ras-cxl-handler.c
+++ b/ras-cxl-handler.c
@@ -1261,7 +1261,7 @@ int ras_cxl_dram_event_handler(struct trace_seq *s,
 /*
  * Memory Module Event Record - MMER
  *
- * CXL res 3.0 section 8.2.9.2.1.3; Table 8-45
+ * CXL res 3.1 section 8.2.9.2.1.3; Table 8-47
  */
 static const char * const cxl_dev_evt_type[] = {
        "Health Status Change",
@@ -1270,21 +1270,33 @@ static const char * const cxl_dev_evt_type[] = {
        "Temperature Change",
        "Data Path Error",
        "LSA Error",
+       "Unrecoverable Internal Sideband Bus Error",
+       "Memory Media FRU Error",
+       "Power Management Fault",
+};
+
+static const char * const cxl_dev_evt_sub_type[] = {
+       "Not Reported",
+       "Invalid Config Data",
+       "Unsupported Config Data",
+       "Unsupported Memory Media FRU",
 };
 
 /*
  * Device Health Information - DHI
  *
- * CXL res 3.0 section 8.2.9.8.3.1; Table 8-100
+ * CXL res 3.1 section 8.2.9.9.3.1; Table 8-133
  */
 #define CXL_DHI_HS_MAINTENANCE_NEEDED                          BIT(0)
 #define CXL_DHI_HS_PERFORMANCE_DEGRADED                                BIT(1)
 #define CXL_DHI_HS_HW_REPLACEMENT_NEEDED                       BIT(2)
+#define CXL_DHI_HS_MEM_CAPACITY_DEGRADED                       BIT(3)
 
 static const struct cxl_event_flags cxl_health_status[] = {
        { .bit = CXL_DHI_HS_MAINTENANCE_NEEDED, .flag = "MAINTENANCE_NEEDED" },
        { .bit = CXL_DHI_HS_PERFORMANCE_DEGRADED, .flag = "PERFORMANCE_DEGRADED" },
        { .bit = CXL_DHI_HS_HW_REPLACEMENT_NEEDED, .flag = "REPLACEMENT_NEEDED" },
+       { .bit = CXL_DHI_HS_MEM_CAPACITY_DEGRADED, .flag = "MEM_CAPACITY_DEGRADED" },
 };
 
 static const char * const cxl_media_status[] = {
@@ -1316,10 +1328,14 @@ static const char * const cxl_one_bit_status[] = {
 #define CXL_DHI_AS_COR_VOL_ERR_CNT(as) (((as) & 0x10) >> 4)
 #define CXL_DHI_AS_COR_PER_ERR_CNT(as) (((as) & 0x20) >> 5)
 
+#define CXL_MMER_VALID_COMPONENT_ID            BIT(0)
+#define CXL_MMER_VALID_COMPONENT_ID_FORMAT     BIT(1)
+
 int ras_cxl_memory_module_event_handler(struct trace_seq *s,
                                        struct tep_record *record,
                                        struct tep_event *event, void *context)
 {
+       int len, i, rc;
        unsigned long long val;
        struct ras_events *ras = context;
        struct ras_cxl_memory_module_event ev;
@@ -1337,6 +1353,15 @@ int ras_cxl_memory_module_event_handler(struct trace_seq *s,
                                              ev.event_type)) <= 0)
                return -1;
 
+       if (tep_get_field_val(s, event, "event_sub_type", record, &val, 1) < 0)
+               return -1;
+       ev.event_sub_type = val;
+       if (trace_seq_printf(s, "event_sub_type:%s ",
+                            get_cxl_type_str(cxl_dev_evt_sub_type,
+                                             ARRAY_SIZE(cxl_dev_evt_sub_type),
+                                             ev.event_sub_type)) <= 0)
+               return -1;
+
        if (tep_get_field_val(s, event, "health_status", record, &val, 1) < 0)
                return -1;
        ev.health_status = val;
@@ -1409,6 +1434,33 @@ int ras_cxl_memory_module_event_handler(struct trace_seq *s,
        if (trace_seq_printf(s, "cor_per_err_cnt:%u ", ev.cor_per_err_cnt) <= 0)
                return -1;
 
+       if (tep_get_field_val(s,  event, "validity_flags", record, &val, 1) < 0)
+               return -1;
+       ev.validity_flags = val;
+
+       if (ev.validity_flags & CXL_MMER_VALID_COMPONENT_ID) {
+               ev.comp_id = tep_get_field_raw(s, event, "comp_id", record, &len, 1);
+               if (!ev.comp_id)
+                       return -1;
+               if (trace_seq_printf(s, "comp_id:") <= 0)
+                       return -1;
+               for (i = 0; i < CXL_EVENT_GEN_MED_COMP_ID_SIZE; i++) {
+                       if (trace_seq_printf(s, "%02x ", ev.comp_id[i]) <= 0)
+                               break;
+               }
+
+               if (ev.validity_flags & CXL_MMER_VALID_COMPONENT_ID_FORMAT) {
+                       if (trace_seq_printf(s, "comp_id_pldm_valid_flags:") <= 0)
+                               return -1;
+                       if (decode_cxl_event_flags(s, ev.comp_id[0], cxl_pldm_comp_id_flags,
+                                                  ARRAY_SIZE(cxl_pldm_comp_id_flags)) < 0)
+                               return -1;
+
+                       rc = ras_cxl_print_component_id(s, ev.comp_id, ev.entity_id, ev.res_id);
+                       if (rc)
+                               return rc;
+               }
+       }
        /* Insert data into the SGBD */
 #ifdef HAVE_SQLITE3
        ras_store_cxl_memory_module_event(ras, &ev);

diff --git a/ras-record.c b/ras-record.c
index 9799d7ea78ba70017257fb804854af2cab4cf80c..eed7aca4a267dced5a8cc54289cee7e17d99571a 100644 (file)
--- a/ras-record.c
+++ b/ras-record.c
@@ -1084,6 +1084,10 @@ static const struct db_fields cxl_memory_module_event_fields[] = {
        { .name = "cor_per_err_cnt",    .type = "INTEGER" },
        { .name = "device_temp",        .type = "INTEGER" },
        { .name = "add_status",         .type = "INTEGER" },
+       { .name = "event_sub_type",     .type = "INTEGER" },
+       { .name = "comp_id",            .type = "BLOB" },
+       { .name = "pldm_entity_id",     .type = "BLOB" },
+       { .name = "pldm_resource_id",   .type = "BLOB" },
 };
 
 static const struct db_table_descriptor cxl_memory_module_event_tab = {
@@ -1116,6 +1120,13 @@ int ras_store_cxl_memory_module_event(struct ras_events *ras,
        sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->cor_per_err_cnt);
        sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->device_temp);
        sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->add_status);
+       sqlite3_bind_int(priv->stmt_cxl_memory_module_event, idx++, ev->event_sub_type);
+       sqlite3_bind_blob(priv->stmt_cxl_memory_module_event, idx++, ev->comp_id,
+                         CXL_EVENT_GEN_MED_COMP_ID_SIZE, NULL);
+       sqlite3_bind_blob(priv->stmt_cxl_memory_module_event, idx++, ev->entity_id,
+                         CXL_PLDM_ENTITY_ID_LEN, NULL);
+       sqlite3_bind_blob(priv->stmt_cxl_memory_module_event, idx++, ev->res_id,
+                         CXL_PLDM_RES_ID_LEN, NULL);
 
        rc = sqlite3_step(priv->stmt_cxl_memory_module_event);
        if (rc != SQLITE_OK && rc != SQLITE_DONE)

diff --git a/ras-record.h b/ras-record.h
index 3aec063cbd9a1db9f6948a2f7f1b0a933bd4d931..5eab62c7f5824ece71411e7182c6c0bfc962ef18 100644 (file)
--- a/ras-record.h
+++ b/ras-record.h
@@ -243,6 +243,7 @@ struct ras_cxl_dram_event {
 struct ras_cxl_memory_module_event {
        struct ras_cxl_event_common_hdr hdr;
        uint8_t event_type;
+       uint8_t event_sub_type;
        uint8_t health_status;
        uint8_t media_status;
        uint8_t life_used;
@@ -251,6 +252,10 @@ struct ras_cxl_memory_module_event {
        uint32_t cor_per_err_cnt;
        int16_t device_temp;
        uint8_t add_status;
+       uint16_t validity_flags;
+       uint8_t *comp_id;
+       uint8_t entity_id[CXL_PLDM_ENTITY_ID_LEN];
+       uint8_t res_id[CXL_PLDM_RES_ID_LEN];
 };
 
 struct ras_mc_event;

diff --git a/ras-report.c b/ras-report.c
index 8e343fc6d2a805fde4b4fafdf1bdf1561bad70d0..453542189810df1dcf69ec1219e491fc5d8895ef 100644 (file)
--- a/ras-report.c
+++ b/ras-report.c
@@ -700,6 +700,7 @@ static int set_cxl_memory_module_event_backtrace(char *buf, struct ras_cxl_memor
                "hdr_length=%u\n"
                "hdr_maint_op_class=%u\n"
                "event_type=%u\n"
+               "event_sub_type=0x%x\n"
                "health_status=%u\n"
                "media_status=%u\n"
                "life_used=%u\n"
@@ -721,6 +722,7 @@ static int set_cxl_memory_module_event_backtrace(char *buf, struct ras_cxl_memor
                ev->hdr.hdr_length,
                ev->hdr.hdr_maint_op_class,
                ev->event_type,
+               ev->event_sub_type,
                ev->health_status,
                ev->media_status,
                ev->life_used,