drm/amd/display: Expose OTG_V_TOTAL_MID for HW Diags

[Why]
Existing HW Features, HW Diags test requested that the
registers be exposed.

[How]
Add V_TOTAL_MID to existing DC structures.
Make sure values are passed down throughout DC
Add Register definition.
Program the additional registers
Add additional Logic for V_TOTAL_CONTROL.

Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 82c07d82e93790f92755cc6678cc74e3e0e59914..87ca5a290d12db168c3b327cb5593878cfbd25c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -291,7 +291,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
                        dc->hwss.set_drr(&pipe,
                                        1,
                                        adjust->v_total_min,
-                                       adjust->v_total_max);
+                                       adjust->v_total_max,
+                                       adjust->v_total_mid,
+                                       adjust->v_total_mid_frame_num);
 
                        ret = true;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index f35826d5d1e5037fdab8d5458bb1bf3836cd865f..0b8700a8a94a684d92fd9d3de062e9235089a06d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -757,6 +757,8 @@ struct crtc_trigger_info {
 struct dc_crtc_timing_adjust {
        uint32_t v_total_min;
        uint32_t v_total_max;
+       uint32_t v_total_mid;
+       uint32_t v_total_mid_frame_num;
 };
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index d2d887972956da05319ec8a89548b7ba2f134cd1..01a924bf477a6d86a933a02b7316d0f168a8c300 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1719,7 +1719,8 @@ void dce110_set_safe_displaymarks(
  ******************************************************************************/
 
 static void set_drr(struct pipe_ctx **pipe_ctx,
-               int num_pipes, int vmin, int vmax)
+               int num_pipes, unsigned int vmin, unsigned int vmax,
+               unsigned int vmid, unsigned int vmid_frame_number)
 {
        int i = 0;
        struct drr_params params = {0};

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 4970543b7f054ad325f4ac0e81621452838a11cc..bd2a83e05625313cc61e71da75e9cf33be8a55e5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2747,7 +2747,8 @@ static void dcn10_optimize_bandwidth(
 }
 
 static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
-               int num_pipes, int vmin, int vmax)
+               int num_pipes, unsigned int vmin, unsigned int vmax,
+               unsigned int vmid, unsigned int vmid_frame_number)
 {
        int i = 0;
        struct drr_params params = {0};
@@ -2756,6 +2757,8 @@ static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
 
        params.vertical_total_max = vmax;
        params.vertical_total_min = vmin;
+       params.vertical_total_mid = vmid;
+       params.vertical_total_mid_frame_num = vmid_frame_number;
 
        /* TODO: If multiple pipes are to be supported, you need
         * some GSL stuff. Static screen triggers may be programmed differently

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index e98e6bab48088a2054cab9f5dfa4f4e3c44e0314..e74a07d03fde913e5aa8d9b5b475f6033f5e7f4a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -850,6 +850,18 @@ void optc1_set_drr(
                params->vertical_total_max > 0 &&
                params->vertical_total_min > 0) {
 
+               if (params->vertical_total_mid != 0) {
+
+                       REG_SET(OTG_V_TOTAL_MID, 0,
+                               OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+                       REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+                                       OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+                                       OTG_VTOTAL_MID_FRAME_NUM,
+                                       (uint8_t)params->vertical_total_mid_frame_num);
+
+               }
+
                REG_SET(OTG_V_TOTAL_MAX, 0,
                        OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 82d91ab54ba581139c3d40addf506222e3b824f2..83575599672e8b67c346a1c273c7e6dca88d6e01 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -54,6 +54,7 @@
        SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
        SRI(OTG_STEREO_STATUS, OTG, inst),\
        SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+       SRI(OTG_V_TOTAL_MID, OTG, inst),\
        SRI(OTG_V_TOTAL_MIN, OTG, inst),\
        SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
        SRI(OTG_TRIGA_CNTL, OTG, inst),\
@@ -125,6 +126,7 @@ struct dcn_optc_registers {
        uint32_t OTG_3D_STRUCTURE_CONTROL;
        uint32_t OTG_STEREO_STATUS;
        uint32_t OTG_V_TOTAL_MAX;
+       uint32_t OTG_V_TOTAL_MID;
        uint32_t OTG_V_TOTAL_MIN;
        uint32_t OTG_V_TOTAL_CONTROL;
        uint32_t OTG_TRIGA_CNTL;
@@ -214,12 +216,15 @@ struct dcn_optc_registers {
        SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
        SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
        SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
        SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
        SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+       SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
        SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
        SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
        SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
@@ -348,9 +353,12 @@ struct dcn_optc_registers {
        type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
        type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
        type OTG_V_TOTAL_MAX;\
+       type OTG_V_TOTAL_MID;\
        type OTG_V_TOTAL_MIN;\
        type OTG_V_TOTAL_MIN_SEL;\
        type OTG_V_TOTAL_MAX_SEL;\
+       type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
+       type OTG_VTOTAL_MID_FRAME_NUM;\
        type OTG_FORCE_LOCK_ON_EVENT;\
        type OTG_SET_V_TOTAL_MIN_MASK_EN;\
        type OTG_SET_V_TOTAL_MIN_MASK;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0fb0a356323b4cdf188b4f7d689a05c2ccbce2d8..161805bb89d3fb63df6527641a1dde14bd991684 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -597,6 +597,8 @@ enum dc_status dcn20_enable_stream_timing(
 
        params.vertical_total_min = stream->adjust.v_total_min;
        params.vertical_total_max = stream->adjust.v_total_max;
+       params.vertical_total_mid = stream->adjust.v_total_mid;
+       params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
        if (pipe_ctx->stream_res.tg->funcs->set_drr)
                pipe_ctx->stream_res.tg->funcs->set_drr(
                        pipe_ctx->stream_res.tg, &params);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index e0713d6d6c8d51382dfc1b70024c6f3bad1e421e..6196cc32356e6685697333b0c0f0e2f94ee38ba9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -59,6 +59,8 @@ struct gsl_params {
 struct drr_params {
        uint32_t vertical_total_min;
        uint32_t vertical_total_max;
+       uint32_t vertical_total_mid;
+       uint32_t vertical_total_mid_frame_num;
        bool immediate_flip;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 68b1185f0636238452a7f8557ec75d4a7ed3a9af..732a93df184414b3cba942071ddbbd079581d117 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -237,7 +237,8 @@ struct hw_sequencer_funcs {
 #endif
 
        void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
-                       int vmin, int vmax);
+                       unsigned int vmin, unsigned int vmax,
+                       unsigned int vmid, unsigned int vmid_frame_number);
 
        void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
                        struct crtc_position *position);