drm/bridge: tc358767: Set default CLRSIPO count

[ Upstream commit 01338bb82fed40a6a234c2b36a92367c8671adf0 ]

The current CLRSIPO count is still marginal and does not work with high
DSI clock rates in burst mode. Increase it further to allow the DSI link
to work at up to 1Gbps lane speed. This returns the counts to defaults
as provided by datasheet.

Fixes: ea6490b02240b ("drm/bridge: tc358767: increase CLRSIPO count")
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20221016003556.406441-1-marex@denx.de
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 2a58eb271f7017084924411e4894ef770d64d5ef..b9b681086fc49cb76e4fd8f61f9631b1e65f13e0 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1264,10 +1264,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc)
        u32 value;
        int ret;
 
-       regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);
-       regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);
-       regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);
-       regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);
+       regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
+       regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
+       regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
+       regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
        regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
        regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
        regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);