AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_END         = 0x19F,
        /* IH: 0x1A0 ~ 0x1AF */
        AMDGPU_DOORBELL_LAYOUT1_IH                      = 0x1A0,
-       /* VCN: 0x1B0 ~ 0x1C2 */
+       /* VCN: 0x1B0 ~ 0x1D4 */
        AMDGPU_DOORBELL_LAYOUT1_VCN_START               = 0x1B0,
-       AMDGPU_DOORBELL_LAYOUT1_VCN_END                 = 0x1C2,
+       AMDGPU_DOORBELL_LAYOUT1_VCN_END                 = 0x1D4,
 
        AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP            = AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START,
        AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP             = AMDGPU_DOORBELL_LAYOUT1_VCN_END,
 
-       AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT          = 0x1C2,
+       AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT          = 0x1D4,
        AMDGPU_DOORBELL_LAYOUT1_INVALID                 = 0xFFFF
 } AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1;
 
 
 
 #include "amdgpu_ras.h"
 
-#define AMDGPU_MAX_JPEG_INSTANCES      2
+#define AMDGPU_MAX_JPEG_INSTANCES      4
 #define AMDGPU_MAX_JPEG_RINGS          8
 
 #define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0)
 
 struct amdgpu_vm;
 
 /* max number of rings */
-#define AMDGPU_MAX_RINGS               96
+#define AMDGPU_MAX_RINGS               102
 #define AMDGPU_MAX_HWIP_RINGS          32
 #define AMDGPU_MAX_GFX_RINGS           2
 #define AMDGPU_MAX_SW_GFX_RINGS         2