powerpc: Remove IBM405 Erratum #77

This erratum is dedicated to IBM 405GP and STB03xxx
which are now gone.

Remove this erratum.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/44dbc08e9034681eb28324cbabc086e97044c36c.1590079969.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/include/asm/asm-405.h b/arch/powerpc/include/asm/asm-405.h
deleted file mode 100644 (file)
index 7270d3a..0000000
--- a/arch/powerpc/include/asm/asm-405.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_POWERPC_ASM_405_H
-#define _ASM_POWERPC_ASM_405_H
-
-#include <asm/asm-const.h>
-
-#ifdef __KERNEL__
-#ifdef CONFIG_IBM405_ERR77
-/* Erratum #77 on the 405 means we need a sync or dcbt before every
- * stwcx.  The old ATOMIC_SYNC_FIX covered some but not all of this.
- */
-#define PPC405_ERR77(ra,rb)    stringify_in_c(dcbt     ra, rb;)
-#define        PPC405_ERR77_SYNC       stringify_in_c(sync;)
-#else
-#define PPC405_ERR77(ra,rb)
-#define PPC405_ERR77_SYNC
-#endif
-#endif
-
-#endif /* _ASM_POWERPC_ASM_405_H */

diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index 31c231ea56b77c4d81bb248bb38041350fc312ef..498785ffc25f33c0c9656d0596be2daed78c11ad 100644 (file)
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -10,7 +10,6 @@
 #include <linux/types.h>
 #include <asm/cmpxchg.h>
 #include <asm/barrier.h>
-#include <asm/asm-405.h>
 
 #define ATOMIC_INIT(i)         { (i) }
 
@@ -47,7 +46,6 @@ static __inline__ void atomic_##op(int a, atomic_t *v)                        \
        __asm__ __volatile__(                                           \
 "1:    lwarx   %0,0,%3         # atomic_" #op "\n"                     \
        #asm_op " %0,%2,%0\n"                                           \
-       PPC405_ERR77(0,%3)                                              \
 "      stwcx.  %0,0,%3 \n"                                             \
 "      bne-    1b\n"                                                   \
        : "=&r" (t), "+m" (v->counter)                                  \
@@ -63,7 +61,6 @@ static inline int atomic_##op##_return_relaxed(int a, atomic_t *v)    \
        __asm__ __volatile__(                                           \
 "1:    lwarx   %0,0,%3         # atomic_" #op "_return_relaxed\n"      \
        #asm_op " %0,%2,%0\n"                                           \
-       PPC405_ERR77(0, %3)                                             \
 "      stwcx.  %0,0,%3\n"                                              \
 "      bne-    1b\n"                                                   \
        : "=&r" (t), "+m" (v->counter)                                  \
@@ -81,7 +78,6 @@ static inline int atomic_fetch_##op##_relaxed(int a, atomic_t *v)     \
        __asm__ __volatile__(                                           \
 "1:    lwarx   %0,0,%4         # atomic_fetch_" #op "_relaxed\n"       \
        #asm_op " %1,%3,%0\n"                                           \
-       PPC405_ERR77(0, %4)                                             \
 "      stwcx.  %1,0,%4\n"                                              \
 "      bne-    1b\n"                                                   \
        : "=&r" (res), "=&r" (t), "+m" (v->counter)                     \
@@ -130,7 +126,6 @@ static __inline__ void atomic_inc(atomic_t *v)
        __asm__ __volatile__(
 "1:    lwarx   %0,0,%2         # atomic_inc\n\
        addic   %0,%0,1\n"
-       PPC405_ERR77(0,%2)
 "      stwcx.  %0,0,%2 \n\
        bne-    1b"
        : "=&r" (t), "+m" (v->counter)
@@ -146,7 +141,6 @@ static __inline__ int atomic_inc_return_relaxed(atomic_t *v)
        __asm__ __volatile__(
 "1:    lwarx   %0,0,%2         # atomic_inc_return_relaxed\n"
 "      addic   %0,%0,1\n"
-       PPC405_ERR77(0, %2)
 "      stwcx.  %0,0,%2\n"
 "      bne-    1b"
        : "=&r" (t), "+m" (v->counter)
@@ -163,7 +157,6 @@ static __inline__ void atomic_dec(atomic_t *v)
        __asm__ __volatile__(
 "1:    lwarx   %0,0,%2         # atomic_dec\n\
        addic   %0,%0,-1\n"
-       PPC405_ERR77(0,%2)\
 "      stwcx.  %0,0,%2\n\
        bne-    1b"
        : "=&r" (t), "+m" (v->counter)
@@ -179,7 +172,6 @@ static __inline__ int atomic_dec_return_relaxed(atomic_t *v)
        __asm__ __volatile__(
 "1:    lwarx   %0,0,%2         # atomic_dec_return_relaxed\n"
 "      addic   %0,%0,-1\n"
-       PPC405_ERR77(0, %2)
 "      stwcx.  %0,0,%2\n"
 "      bne-    1b"
        : "=&r" (t), "+m" (v->counter)
@@ -220,7 +212,6 @@ static __inline__ int atomic_fetch_add_unless(atomic_t *v, int a, int u)
        cmpw    0,%0,%3 \n\
        beq     2f \n\
        add     %0,%2,%0 \n"
-       PPC405_ERR77(0,%2)
 "      stwcx.  %0,0,%1 \n\
        bne-    1b \n"
        PPC_ATOMIC_EXIT_BARRIER
@@ -251,7 +242,6 @@ static __inline__ int atomic_inc_not_zero(atomic_t *v)
        cmpwi   0,%0,0\n\
        beq-    2f\n\
        addic   %1,%0,1\n"
-       PPC405_ERR77(0,%2)
 "      stwcx.  %1,0,%2\n\
        bne-    1b\n"
        PPC_ATOMIC_EXIT_BARRIER
@@ -280,7 +270,6 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
        cmpwi   %0,1\n\
        addi    %0,%0,-1\n\
        blt-    2f\n"
-       PPC405_ERR77(0,%1)
 "      stwcx.  %0,0,%1\n\
        bne-    1b"
        PPC_ATOMIC_EXIT_BARRIER

diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 28dcf822294348d5d3f03a5134af4e52945b23fd..4a4d3afd5340658e3a7285410e86b56415722ac7 100644 (file)
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -41,7 +41,6 @@
 #include <linux/compiler.h>
 #include <asm/asm-compat.h>
 #include <asm/synch.h>
-#include <asm/asm-405.h>
 
 /* PPC bit number conversion */
 #define PPC_BITLSHIFT(be)      (BITS_PER_LONG - 1 - (be))
@@ -73,7 +72,6 @@ static inline void fn(unsigned long mask,     \
        prefix                                  \
 "1:"   PPC_LLARX(%0,0,%3,0) "\n"               \
        stringify_in_c(op) "%0,%0,%2\n"         \
-       PPC405_ERR77(0,%3)                      \
        PPC_STLCX "%0,0,%3\n"                   \
        "bne- 1b\n"                             \
        : "=&r" (old), "+m" (*p)                \
@@ -119,7 +117,6 @@ static inline unsigned long fn(                     \
        prefix                                          \
 "1:"   PPC_LLARX(%0,0,%3,eh) "\n"                      \
        stringify_in_c(op) "%1,%0,%2\n"                 \
-       PPC405_ERR77(0,%3)                              \
        PPC_STLCX "%1,0,%3\n"                           \
        "bne- 1b\n"                                     \
        postfix                                         \
@@ -175,7 +172,6 @@ clear_bit_unlock_return_word(int nr, volatile unsigned long *addr)
        PPC_RELEASE_BARRIER
 "1:"   PPC_LLARX(%0,0,%3,0) "\n"
        "andc %1,%0,%2\n"
-       PPC405_ERR77(0,%3)
        PPC_STLCX "%1,0,%3\n"
        "bne- 1b\n"
        : "=&r" (old), "=&r" (t)

diff --git a/arch/powerpc/include/asm/cmpxchg.h b/arch/powerpc/include/asm/cmpxchg.h
index 27183871eb3bf667a625b6cbb987070802132f80..cf091c4c22e5357b3f1aa8ee2affe571b137e87f 100644 (file)
--- a/arch/powerpc/include/asm/cmpxchg.h
+++ b/arch/powerpc/include/asm/cmpxchg.h
@@ -6,7 +6,6 @@
 #include <linux/compiler.h>
 #include <asm/synch.h>
 #include <linux/bug.h>
-#include <asm/asm-405.h>
 
 #ifdef __BIG_ENDIAN
 #define BITOFF_CAL(size, off)  ((sizeof(u32) - size - off) * BITS_PER_BYTE)
@@ -29,7 +28,6 @@ static inline u32 __xchg_##type##sfx(volatile void *p, u32 val)       \
 "1:    lwarx   %0,0,%3\n"                                      \
 "      andc    %1,%0,%5\n"                                     \
 "      or      %1,%1,%4\n"                                     \
-       PPC405_ERR77(0,%3)                                      \
 "      stwcx.  %1,0,%3\n"                                      \
 "      bne-    1b\n"                                           \
        : "=&r" (prev), "=&r" (tmp), "+m" (*(u32*)p)            \
@@ -60,7 +58,6 @@ u32 __cmpxchg_##type##sfx(volatile void *p, u32 old, u32 new) \
 "      bne-    2f\n"                                           \
 "      andc    %1,%0,%6\n"                                     \
 "      or      %1,%1,%5\n"                                     \
-       PPC405_ERR77(0,%3)                                      \
 "      stwcx.  %1,0,%3\n"                                      \
 "      bne-    1b\n"                                           \
        br2                                                     \
@@ -92,7 +89,6 @@ __xchg_u32_local(volatile void *p, unsigned long val)
 
        __asm__ __volatile__(
 "1:    lwarx   %0,0,%2 \n"
-       PPC405_ERR77(0,%2)
 "      stwcx.  %3,0,%2 \n\
        bne-    1b"
        : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
@@ -109,7 +105,6 @@ __xchg_u32_relaxed(u32 *p, unsigned long val)
 
        __asm__ __volatile__(
 "1:    lwarx   %0,0,%2\n"
-       PPC405_ERR77(0, %2)
 "      stwcx.  %3,0,%2\n"
 "      bne-    1b"
        : "=&r" (prev), "+m" (*p)
@@ -127,7 +122,6 @@ __xchg_u64_local(volatile void *p, unsigned long val)
 
        __asm__ __volatile__(
 "1:    ldarx   %0,0,%2 \n"
-       PPC405_ERR77(0,%2)
 "      stdcx.  %3,0,%2 \n\
        bne-    1b"
        : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
@@ -144,7 +138,6 @@ __xchg_u64_relaxed(u64 *p, unsigned long val)
 
        __asm__ __volatile__(
 "1:    ldarx   %0,0,%2\n"
-       PPC405_ERR77(0, %2)
 "      stdcx.  %3,0,%2\n"
 "      bne-    1b"
        : "=&r" (prev), "+m" (*p)
@@ -229,7 +222,6 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 "1:    lwarx   %0,0,%2         # __cmpxchg_u32\n\
        cmpw    0,%0,%3\n\
        bne-    2f\n"
-       PPC405_ERR77(0,%2)
 "      stwcx.  %4,0,%2\n\
        bne-    1b"
        PPC_ATOMIC_EXIT_BARRIER
@@ -252,7 +244,6 @@ __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
 "1:    lwarx   %0,0,%2         # __cmpxchg_u32\n\
        cmpw    0,%0,%3\n\
        bne-    2f\n"
-       PPC405_ERR77(0,%2)
 "      stwcx.  %4,0,%2\n\
        bne-    1b"
        "\n\
@@ -273,7 +264,6 @@ __cmpxchg_u32_relaxed(u32 *p, unsigned long old, unsigned long new)
 "1:    lwarx   %0,0,%2         # __cmpxchg_u32_relaxed\n"
 "      cmpw    0,%0,%3\n"
 "      bne-    2f\n"
-       PPC405_ERR77(0, %2)
 "      stwcx.  %4,0,%2\n"
 "      bne-    1b\n"
 "2:"
@@ -301,7 +291,6 @@ __cmpxchg_u32_acquire(u32 *p, unsigned long old, unsigned long new)
 "1:    lwarx   %0,0,%2         # __cmpxchg_u32_acquire\n"
 "      cmpw    0,%0,%3\n"
 "      bne-    2f\n"
-       PPC405_ERR77(0, %2)
 "      stwcx.  %4,0,%2\n"
 "      bne-    1b\n"
        PPC_ACQUIRE_BARRIER

diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
index f187bb5e524e17b68293455d8b4574b5bf270735..e93ee3202e4c174bad59e6c4559c312f87bcdf81 100644 (file)
--- a/arch/powerpc/include/asm/futex.h
+++ b/arch/powerpc/include/asm/futex.h
@@ -8,14 +8,12 @@
 #include <linux/uaccess.h>
 #include <asm/errno.h>
 #include <asm/synch.h>
-#include <asm/asm-405.h>
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
   __asm__ __volatile ( \
        PPC_ATOMIC_ENTRY_BARRIER \
 "1:    lwarx   %0,0,%2\n" \
        insn \
-       PPC405_ERR77(0, %2) \
 "2:    stwcx.  %1,0,%2\n" \
        "bne-   1b\n" \
        PPC_ATOMIC_EXIT_BARRIER \
@@ -82,7 +80,6 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 "1:     lwarx   %1,0,%3         # futex_atomic_cmpxchg_inatomic\n\
         cmpw    0,%1,%4\n\
         bne-    3f\n"
-        PPC405_ERR77(0,%3)
 "2:     stwcx.  %5,0,%3\n\
         bne-    1b\n"
         PPC_ATOMIC_EXIT_BARRIER

diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 46cd5428fc52cb8d58cd0474e2ed7358eb1066e0..639f3b3713ec7a48942aac5745812df542f8a214 100644 (file)
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -9,7 +9,6 @@
 #include <linux/sched.h>
 #include <linux/threads.h>
 #include <asm/mmu.h>                   /* For sub-arch specific PPC_PIN_SIZE */
-#include <asm/asm-405.h>
 
 #ifdef CONFIG_44x
 extern int icache_44x_need_flush;

diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index 860228e917dce1d4e8279a4b1a1f97834e606d2c..2d620896cdaee3a22850571148dfc028288bb325 100644 (file)
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -23,7 +23,6 @@
 #endif
 #include <asm/synch.h>
 #include <asm/ppc-opcode.h>
-#include <asm/asm-405.h>
 
 #ifdef CONFIG_PPC64
 /* use 0x800000yy when locked, where yy == CPU number */
@@ -210,7 +209,6 @@ static inline long __arch_read_trylock(arch_rwlock_t *rw)
        __DO_SIGN_EXTEND
 "      addic.          %0,%0,1\n\
        ble-            2f\n"
-       PPC405_ERR77(0,%1)
 "      stwcx.          %0,0,%1\n\
        bne-            1b\n"
        PPC_ACQUIRE_BARRIER
@@ -234,7 +232,6 @@ static inline long __arch_write_trylock(arch_rwlock_t *rw)
 "1:    " PPC_LWARX(%0,0,%2,1) "\n\
        cmpwi           0,%0,0\n\
        bne-            2f\n"
-       PPC405_ERR77(0,%1)
 "      stwcx.          %1,0,%2\n\
        bne-            1b\n"
        PPC_ACQUIRE_BARRIER
@@ -292,7 +289,6 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
        PPC_RELEASE_BARRIER
 "1:    lwarx           %0,0,%1\n\
        addic           %0,%0,-1\n"
-       PPC405_ERR77(0,%1)
 "      stwcx.          %0,0,%1\n\
        bne-            1b"
        : "=&r"(tmp)

diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 8420abd4ea1ce8bf7400bf3b68389bc85ff562ea..a7b261440d59ed04d8d1ebc7bb4c45691758f4e6 100644 (file)
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -28,7 +28,6 @@
 #include <asm/unistd.h>
 #include <asm/ptrace.h>
 #include <asm/export.h>
-#include <asm/asm-405.h>
 #include <asm/feature-fixups.h>
 #include <asm/barrier.h>
 #include <asm/kup.h>
@@ -541,9 +540,6 @@ syscall_exit_work:
        addi    r12,r2,TI_FLAGS
 3:     lwarx   r8,0,r12
        andc    r8,r8,r11
-#ifdef CONFIG_IBM405_ERR77
-       dcbt    0,r12
-#endif
        stwcx.  r8,0,r12
        bne-    3b
        
@@ -918,9 +914,6 @@ resume_kernel:
        addi    r5,r2,TI_FLAGS
 0:     lwarx   r8,0,r5
        andc    r8,r8,r11
-#ifdef CONFIG_IBM405_ERR77
-       dcbt    0,r5
-#endif
        stwcx.  r8,0,r5
        bne-    0b
 1:
@@ -997,7 +990,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
        mtspr   SPRN_XER,r10
        mtctr   r11
 
-       PPC405_ERR77(0,r1)
 BEGIN_FTR_SECTION
        lwarx   r11,0,r1
 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
@@ -1066,7 +1058,6 @@ exc_exit_start:
        lwz     r1,GPR1(r1)
        .globl exc_exit_restart_end
 exc_exit_restart_end:
-       PPC405_ERR77_SYNC
        rfi
        b       .                       /* prevent prefetch past rfi */
 
@@ -1109,7 +1100,6 @@ exc_exit_restart_end:
        lwz     r11,_CTR(r1);                                           \
        mtspr   SPRN_XER,r10;                                           \
        mtctr   r11;                                                    \
-       PPC405_ERR77(0,r1);                                             \
        stwcx.  r0,0,r1;                /* to clear the reservation */  \
        lwz     r11,_LINK(r1);                                          \
        mtlr    r11;                                                    \
@@ -1129,7 +1119,6 @@ exc_exit_restart_end:
        lwz     r10,GPR10(r1);                                          \
        lwz     r11,GPR11(r1);                                          \
        lwz     r1,GPR1(r1);                                            \
-       PPC405_ERR77_SYNC;                                              \
        exc_lvl_rfi;                                                    \
        b       .;              /* prevent prefetch past exc_lvl_rfi */
 

diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index a78cacea0be087c0376cf3c2ec7b94de515a3136..75238897093dc93fb8ee216d26ca4ed910fef148 100644 (file)
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -36,7 +36,6 @@
 #include <asm/asm-offsets.h>
 #include <asm/ptrace.h>
 #include <asm/export.h>
-#include <asm/asm-405.h>
 
 #include "head_32.h"
 
@@ -487,7 +486,6 @@ _ENTRY(saved_ksp_limit)
        lwz     r12,GPR12(r11)
        lwz     r10,crit_r10@l(0)
        lwz     r11,crit_r11@l(0)
-       PPC405_ERR77_SYNC
        rfci
        b       .
 
@@ -569,7 +567,6 @@ finish_tlb_load:
        mfspr   r12, SPRN_SPRG_SCRATCH3
        mfspr   r11, SPRN_SPRG_SCRATCH1
        mfspr   r10, SPRN_SPRG_SCRATCH0
-       PPC405_ERR77_SYNC
        rfi                     /* Should sync shadow TLBs */
        b       .               /* prevent prefetch past rfi */
 

diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index ebe2834764614188a9c28163e824348c03ea0923..e3e5217c9822278f17c1171ee1ece14a8182e1b6 100644 (file)
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -69,12 +69,6 @@ config PPC4xx_GPIO
        help
          Enable gpiolib support for ppc40x based boards
 
-# 40x errata/workaround config symbols, selected by the CPU models above
-
-# All 405-based cores up until the 405GPR and 405EP have this errata.
-config IBM405_ERR77
-       bool
-
 config APM8018X
        bool "APM8018X"
        depends on 40x