drm/i915: pass dev_priv explicitly to PIPESRC

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPESRC register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ac1959b7038d6fedb4777dcf2b961de901fb8880.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 5c8778865156fdae66385eaff2316b6231f04dde..864d94406894d841fd626aeb72911b7d4fd83285 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -1053,7 +1053,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
        drm_WARN_ON(&dev_priv->drm, offset != 0);
 
-       val = intel_de_read(dev_priv, PIPESRC(pipe));
+       val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe));
        fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
        fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
 

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 993eb0935f6b8b68b22169d7edd0a21fca15ed50..81ae72648e8e8bb04aede55620073de0278dc058 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2784,7 +2784,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
        /* pipesrc controls the size that is scaled from, which should
         * always be the user's requested size.
         */
-       intel_de_write(dev_priv, PIPESRC(pipe),
+       intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
                       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
 }
 
@@ -2878,7 +2878,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
        struct drm_i915_private *dev_priv = to_i915(dev);
        u32 tmp;
 
-       tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
+       tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));
 
        drm_rect_init(&pipe_config->pipe_src, 0, 0,
                      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
@@ -8204,7 +8204,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
                       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
        intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
                       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
-       intel_de_write(dev_priv, PIPESRC(pipe),
+       intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
                       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
 
        intel_de_write(dev_priv, FP0(pipe), fp);

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 0afde865a7deb3e911cb30d9f9183781fdf87330..c454e25b2b0f4484f50bd83e37c319dea4131047 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -267,11 +267,11 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
                (_PRI_PLANE_STRIDE_MASK >> 6) :
                _PRI_PLANE_STRIDE_MASK, plane->bpp);
 
-       plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
+       plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >>
                _PIPE_H_SRCSZ_SHIFT;
        plane->width += 1;
-       plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
-                       _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
+       plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) &
+                        _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
        plane->height += 1;     /* raw height is one minus the real value */
 
        val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f6f2bb06f35289bd48eba1c462f17f1529638de..8e312aa8ca71daf98811282b8c981e8a3bcca462 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1144,7 +1144,7 @@
 #define TRANS_VSYNC(dev_priv, trans)   _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(dev_priv, trans)               _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(dev_priv, trans)      _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
-#define PIPESRC(pipe)          _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
+#define PIPESRC(dev_priv, pipe)                _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
 #define TRANS_MULT(trans)      _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
 /* VRR registers */

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 5abae7df0bfecaae43e79e891172a5ba589e8666..ff561a1e0fd341a61537393647808ef97b9d5e64 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -239,7 +239,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
-       MMIO_D(PIPESRC(TRANSCODER_A));
+       MMIO_D(PIPESRC(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
@@ -248,7 +248,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
-       MMIO_D(PIPESRC(TRANSCODER_B));
+       MMIO_D(PIPESRC(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
@@ -257,7 +257,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
        MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
-       MMIO_D(PIPESRC(TRANSCODER_C));
+       MMIO_D(PIPESRC(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));