#define CAP3                   0x10
 #define CAP4                   0x14
 #define ECCTL2                 0x2A
+#define ECCTL2_APWM_POL_LOW    BIT(10)
 #define ECCTL2_APWM_MODE       BIT(9)
 #define ECCTL2_SYNC_SEL_DISA   (BIT(7) | BIT(6))
 #define ECCTL2_TSCTR_FREERUN   BIT(4)
        return 0;
 }
 
+static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
+               enum pwm_polarity polarity)
+{
+       struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
+       unsigned short reg_val;
+
+       pm_runtime_get_sync(pc->chip.dev);
+       reg_val = readw(pc->mmio_base + ECCTL2);
+       if (polarity == PWM_POLARITY_INVERSED)
+               /* Duty cycle defines LOW period of PWM */
+               reg_val |= ECCTL2_APWM_POL_LOW;
+       else
+               /* Duty cycle defines HIGH period of PWM */
+               reg_val &= ~ECCTL2_APWM_POL_LOW;
+
+       writew(reg_val, pc->mmio_base + ECCTL2);
+       pm_runtime_put_sync(pc->chip.dev);
+       return 0;
+}
+
 static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
        struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
 static const struct pwm_ops ecap_pwm_ops = {
        .free           = ecap_pwm_free,
        .config         = ecap_pwm_config,
+       .set_polarity   = ecap_pwm_set_polarity,
        .enable         = ecap_pwm_enable,
        .disable        = ecap_pwm_disable,
        .owner          = THIS_MODULE,