ret = PTR_ERR(backend->mod_clk);
                goto err_disable_bus_clk;
        }
+
+       ret = clk_set_rate_exclusive(backend->mod_clk, 300000000);
+       if (ret) {
+               dev_err(dev, "Couldn't set the module clock frequency\n");
+               goto err_disable_bus_clk;
+       }
+
        clk_prepare_enable(backend->mod_clk);
 
        backend->ram_clk = devm_clk_get(dev, "ram");
 err_disable_ram_clk:
        clk_disable_unprepare(backend->ram_clk);
 err_disable_mod_clk:
+       clk_rate_exclusive_put(backend->mod_clk);
        clk_disable_unprepare(backend->mod_clk);
 err_disable_bus_clk:
        clk_disable_unprepare(backend->bus_clk);
                sun4i_backend_free_sat(dev);
 
        clk_disable_unprepare(backend->ram_clk);
+       clk_rate_exclusive_put(backend->mod_clk);
        clk_disable_unprepare(backend->mod_clk);
        clk_disable_unprepare(backend->bus_clk);
        reset_control_assert(backend->reset);