arm64: dts: qcom: qcm2290: Add uart3 node

Add node to support uart3.

Signed-off-by: Wojciech Slenska <wojciech.slenska@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241112124651.215537-1-wojciech.slenska@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index f0746123e594d5ce5cc314c956eaca11556a9211..496e493c5845c7d75508ecfb8e0ffc37863303ff 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
@@ -550,6 +550,13 @@
                                bias-disable;
                        };
 
+                       qup_uart3_default: qup-uart3-default-state {
+                               pins = "gpio8", "gpio9", "gpio10", "gpio11";
+                               function = "qup3";
+                               drive-strength = <2>;
+                               bias-disable;
+                       };
+
                        qup_uart4_default: qup-uart4-default-state {
                                pins = "gpio12", "gpio13";
                                function = "qup4";
@@ -1239,6 +1246,23 @@
                                status = "disabled";
                        };
 
+                       uart3: serial@4a8c000 {
+                               compatible = "qcom,geni-uart";
+                               reg = <0x0 0x04a8c000 0x0 0x4000>;
+                               interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+                               clock-names = "se";
+                               pinctrl-0 = <&qup_uart3_default>;
+                               pinctrl-names = "default";
+                               interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+                                                &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+                                               <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+                                                &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+                               interconnect-names = "qup-core",
+                                                    "qup-config";
+                               status = "disabled";
+                       };
+
                        i2c4: i2c@4a90000 {
                                compatible = "qcom,geni-i2c";
                                reg = <0x0 0x04a90000 0x0 0x4000>;