MIPS: Convert R4600_V2_HIT_CACHEOP into a config option

Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 714cd81a779c7bf669ad3046ae67e5e4e3ea64fc..e4198c5c2aa809a6bdba609a7041d78c705a7ba5 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -640,6 +640,7 @@ config SGI_IP22
        select SYS_SUPPORTS_BIG_ENDIAN
        select WAR_R4600_V1_INDEX_ICACHEOP
        select WAR_R4600_V1_HIT_CACHEOP
+       select WAR_R4600_V2_HIT_CACHEOP
        select MIPS_L1_CACHE_SHIFT_7
        help
          This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -877,6 +878,7 @@ config SNI_RM
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
        select SYS_SUPPORTS_LITTLE_ENDIAN
+       select WAR_R4600_V2_HIT_CACHEOP
        help
          The SNI RM200/300/400 are MIPS-based machines manufactured by
          Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -2643,6 +2645,18 @@ config WAR_R4600_V1_INDEX_ICACHEOP
 config WAR_R4600_V1_HIT_CACHEOP
        bool
 
+# Writeback and invalidate the primary cache dcache before DMA.
+#
+# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
+# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
+# operate correctly if the internal data cache refill buffer is empty.  These
+# CACHE instructions should be separated from any potential data cache miss
+# by a load instruction to an uncached address to empty the response buffer."
+# (Revision 2.0 device errata from IDT available on https://www.idt.com/
+# in .pdf format.)
+config WAR_R4600_V2_HIT_CACHEOP
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 915ce0352c20412bfcbca011556771d38c1f1d00..4bc396d0fdd986188434a76b16d27f0cafba010b 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,6 @@
 #ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 44d14be2e1e599ec11426e9013bda2a9eec77e2c..4d46a880b8320d638ebe57675f2ed1ecdea6edea 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MACH_GENERIC_WAR_H
 #define __ASM_MACH_GENERIC_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 9154c54d428a98d4efec9863e43d693f5267479e..a5a1c41df74e2aa5b971fd061bc6f8ec28bd6c29 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -8,11 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP22_WAR_H
 #define __ASM_MIPS_MACH_IP22_WAR_H
 
-/*
- * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
- */
-
-#define R4600_V2_HIT_CACHEOP_WAR       1
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index e7c070c85b7cd56ee30de54790d44b0da28c74eb..5891d506cffdf38b4f4202683369ed717efeff98 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP27_WAR_H
 #define __ASM_MIPS_MACH_IP27_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 22d9f78bf552a594a8c527f29440882714bb5ac0..346fc567ebb347dfbd8ef1d809f3d52e4066c08d 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP28_WAR_H
 #define __ASM_MIPS_MACH_IP28_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 1400b030982eff08a53554f17814dc90b98f786b..f887a0a53e183433956459ab87ab60dad06173f1 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_MIPS_MACH_IP30_WAR_H
 #define __ASM_MIPS_MACH_IP30_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index f91f4eddce8f0a846634dbc27db1d78bcaccdf4c..980dbd34355c142b859033f6fcab5aa07bb7d3a1 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP32_WAR_H
 #define __ASM_MIPS_MACH_IP32_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index a4d5d0926e81d808d959362547150df781541df2..29f56803e3e5593a8545ca1a3b44afbb88d10516 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       1

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 82ce2d313eed82c0d6dab172e7ed51a5babe0510..749787bb6c8e260b25b86153e92f00c3376a1f11 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       1

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index 192ec3358ad0fd103967c416f6b6d00fdb52578e..aded634ccb01a611bbb3967b9e8c5e7bb0bb2d75 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -8,11 +8,6 @@
 #ifndef __ASM_MIPS_MACH_RM_WAR_H
 #define __ASM_MIPS_MACH_RM_WAR_H
 
-/*
- * The RM200C seems to have been shipped only with V2.0 R4600s
- */
-
-#define R4600_V2_HIT_CACHEOP_WAR       1
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index bf793d36c890e9a22497c2fd8ab1ab198208e1b3..78fd2ad4930bcbd2956173fb0e8aebee6ed8e615 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -8,8 +8,6 @@
 #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
 #define __ASM_MIPS_MACH_SIBYTE_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
-
 #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
 
 #ifndef __ASSEMBLY__

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index 7da1a3ea54c704d4189b748067b762bdbf0fff89..0b1666e0391a935f4816c6d500f44407a9128c70 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
 #define __ASM_MIPS_MACH_TX49XX_WAR_H
 
-#define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index d336a0e57093f2cba687383a89f9736a0e078ef5..37092c2c68e16b1eb3b012c66fa98d8591fee8c5 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -72,21 +72,6 @@
 #define DADDI_WAR 0
 #endif
 
-/*
- * Writeback and invalidate the primary cache dcache before DMA.
- *
- * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
- * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
- * operate correctly if the internal data cache refill buffer is empty.         These
- * CACHE instructions should be separated from any potential data cache miss
- * by a load instruction to an uncached address to empty the response buffer."
- * (Revision 2.0 device errata from IDT available on https://www.idt.com/
- * in .pdf format.)
- */
-#ifndef R4600_V2_HIT_CACHEOP_WAR
-#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
-#endif
-
 /*
  * Workaround for the Sibyte M3 errata the text of which can be found at
  *

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 814a295a2df27657ef9218f29622d3e6950de5fb..df09a3653c4f986ed0ef8deddaa16f22a7daf11b 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -130,7 +130,8 @@ struct bcache_ops *bcops = &no_sc_ops;
 
 #define R4600_HIT_CACHEOP_WAR_IMPL                                     \
 do {                                                                   \
-       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
+       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&              \
+           cpu_is_r4600_v2_x())                                        \
                *(volatile unsigned long *)CKSEG1;                      \
        if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP))                                        \
                __asm__ __volatile__("nop;nop;nop;nop");                \

diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index ecad11f5c67ce08d47b620e1df58af2747442e86..504bc4047c4cfe7cfb432c57cd025d9001b8c093 100644 (file)
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -258,7 +258,8 @@ static inline void build_clear_pref(u32 **buf, int off)
                                uasm_i_nop(buf);
                        }
 
-                       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
+                           cpu_is_r4600_v2_x())
                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@@ -303,7 +304,7 @@ void build_clear_page(void)
        else
                uasm_i_ori(&buf, A2, A0, off);
 
-       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
                uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
 
        off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
@@ -411,7 +412,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
                                uasm_i_nop(buf);
                        }
 
-                       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) &&
+                           cpu_is_r4600_v2_x())
                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
@@ -455,7 +457,7 @@ void build_copy_page(void)
        else
                uasm_i_ori(&buf, A2, A0, off);
 
-       if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+       if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && cpu_is_r4600_v2_x())
                uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
 
        off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *