drm/amd/display: move dispclk vco freq to clk mgr base

This value will be needed by dml and therefore should be externally
accessible.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index c5c8c4901eedb0e6eae8a062056e1741e653fd6a..26db1c5d4e4d2619dea1ba09c4d8ad2f92678cd9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -147,7 +147,7 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
 
        /* Calculate the current DFS clock, in kHz.*/
        dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-               * clk_mgr->dentist_vco_freq_khz) / target_div;
+               * clk_mgr->base.dentist_vco_freq_khz) / target_div;
 
        return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
 }
@@ -239,7 +239,7 @@ int dce_set_clock(
        /* Make sure requested clock isn't lower than minimum threshold*/
        if (requested_clk_khz > 0)
                requested_clk_khz = max(requested_clk_khz,
-                               clk_mgr_dce->dentist_vco_freq_khz / 64);
+                               clk_mgr_dce->base.dentist_vco_freq_khz / 64);
 
        /* Prepare to program display clock*/
        pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
@@ -276,11 +276,11 @@ static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce)
        int i;
 
        if (bp->integrated_info)
-               clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
-       if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
-               clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
-               if (clk_mgr_dce->dentist_vco_freq_khz == 0)
-                       clk_mgr_dce->dentist_vco_freq_khz = 3600000;
+               clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+       if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) {
+               clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+               if (clk_mgr_dce->base.dentist_vco_freq_khz == 0)
+                       clk_mgr_dce->base.dentist_vco_freq_khz = 3600000;
        }
 
        /*update the maximum display clock for each power state*/

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 7c746ef1e32ea0a54ba37b560f8c0aad6a76c260..a6c46e903ff92ce52e4402b0eabec85e715c54cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -81,7 +81,7 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
        /* Make sure requested clock isn't lower than minimum threshold*/
        if (requested_clk_khz > 0)
                requested_clk_khz = max(requested_clk_khz,
-                               clk_mgr_dce->dentist_vco_freq_khz / 62);
+                               clk_mgr_dce->base.dentist_vco_freq_khz / 62);
 
        dce_clk_params.target_clock_frequency = requested_clk_khz;
        dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
@@ -135,7 +135,7 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
        /* Make sure requested clock isn't lower than minimum threshold*/
        if (requested_clk_khz > 0)
                requested_clk_khz = max(requested_clk_khz,
-                               clk_mgr->dentist_vco_freq_khz / 62);
+                               clk_mgr->base.dentist_vco_freq_khz / 62);
 
        dce_clk_params.target_clock_frequency = requested_clk_khz;
        dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 5b3d36d418228cd7fa1d76831e15abe21357f173..3fab9296918ab3f8ec0193dbe7dd6409c7450448 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -269,11 +269,11 @@ void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_
        clk_mgr->base.dprefclk_khz = 600000;
 
        if (bp->integrated_info)
-               clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
-       if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
-               clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
-               if (clk_mgr->dentist_vco_freq_khz == 0)
-                       clk_mgr->dentist_vco_freq_khz = 3600000;
+               clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
+       if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {
+               clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
+               if (clk_mgr->base.dentist_vco_freq_khz == 0)
+                       clk_mgr->base.dentist_vco_freq_khz = 3600000;
        }
 
        if (!debug->disable_dfs_bypass && bp->integrated_info)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 69daddbfbf29c4fee51590f62579aa05831e2f5c..607d8afc56ec13b18f36c91cfdcccc0abdccf356 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -121,9 +121,9 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
 {
        int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-                       * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
+                       * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
        int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-                       * clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
+                       * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
 
        uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
        uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
@@ -412,7 +412,7 @@ void dcn20_clk_mgr_construct(
 
        if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
                dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
-               clk_mgr->dentist_vco_freq_khz = 3850000;
+               clk_mgr->base.dentist_vco_freq_khz = 3850000;
 
        } else {
                /* DFS Slice 2 should be used for DPREFCLK */
@@ -436,15 +436,15 @@ void dcn20_clk_mgr_construct(
                pll_req = dc_fixpt_mul_int(pll_req, 100000);
 
                /* integer part is now VCO frequency in kHz */
-               clk_mgr->dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
+               clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
 
                /* in case we don't get a value from the register, use default */
-               if (clk_mgr->dentist_vco_freq_khz == 0)
-                       clk_mgr->dentist_vco_freq_khz = 3850000;
+               if (clk_mgr->base.dentist_vco_freq_khz == 0)
+                       clk_mgr->base.dentist_vco_freq_khz = 3850000;
 
                /* Calculate the DPREFCLK in kHz.*/
                clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
-                       * clk_mgr->dentist_vco_freq_khz) / target_div;
+                       * clk_mgr->base.dentist_vco_freq_khz) / target_div;
        }
        //Integrated_info table does not exist on dGPU projects so should not be referenced
        //anywhere in code for dGPUs.

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 6212b407cd01c060b0710dd1b1af7d2f210cbe4d..e8b8ee4f1b1ee5154ec9f11411766695d8fb05ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -472,7 +472,7 @@ struct clk_bw_params rn_bw_params = {
        }
 };
 
-void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
+static void rn_build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
 {
        int i, num_valid_sets;
 
@@ -542,7 +542,7 @@ static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsi
        return 0;
 }
 
-void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
+static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
 {
        int i, j = 0;
 
@@ -628,17 +628,17 @@ void rn_clk_mgr_construct(
 
        if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
                dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
-               clk_mgr->dentist_vco_freq_khz = 3600000;
+               clk_mgr->base.dentist_vco_freq_khz = 3600000;
                clk_mgr->base.dprefclk_khz = 600000;
        } else {
                struct clk_log_info log_info = {0};
 
                /* TODO: Check we get what we expect during bringup */
-               clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
+               clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 
                /* in case we don't get a value from the register, use default */
-               if (clk_mgr->dentist_vco_freq_khz == 0)
-                       clk_mgr->dentist_vco_freq_khz = 3600000;
+               if (clk_mgr->base.dentist_vco_freq_khz == 0)
+                       clk_mgr->base.dentist_vco_freq_khz = 3600000;
 
                rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
                /* Convert dprefclk units from MHz to KHz */

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
index 761bfda970a5d620881300cb456a2f13ec3eb52a..e4322fa5475b6f0a23a0fd82bde2c513143f04c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
@@ -33,13 +33,6 @@ struct rn_clk_registers {
        uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
 };
 
-void rn_build_watermark_ranges(
-               struct clk_bw_params *bw_params,
-               struct pp_smu_wm_range_sets *ranges);
-void rn_clk_mgr_helper_populate_bw_params(
-               struct clk_bw_params *bw_params,
-               struct dpm_clocks *clock_table,
-               struct hw_asic_id *asic_id);
 void rn_clk_mgr_construct(struct dc_context *ctx,
                struct clk_mgr_internal *clk_mgr,
                struct pp_smu_funcs *pp_smu,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 4f9c3538fa8c488a1ab19bf9bee808a37b762aac..db3fb57bf244e2a4076db9cf60b48d6601b2a5f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3002,7 +3002,7 @@ static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
        }
 }
 
-static void cap_soc_clocks(
+void dcn20_cap_soc_clocks(
                struct _vcs_dpi_soc_bounding_box_st *bb,
                struct pp_smu_nv_clock_table max_clocks)
 {
@@ -3069,7 +3069,7 @@ static void cap_soc_clocks(
        }
 }
 
-static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
+void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
                struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
 {
        struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
@@ -3127,7 +3127,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
        bb->clock_limits[num_calculated_states].state = bb->num_states;
 }
 
-static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
+void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
 {
        kernel_fpu_begin();
        if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
@@ -3326,14 +3326,14 @@ static bool init_soc_bounding_box(struct dc *dc,
                }
 
                if (clock_limits_available && uclk_states_available && num_states)
-                       update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
+                       dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
                else if (clock_limits_available)
-                       cap_soc_clocks(loaded_bb, max_clocks);
+                       dcn20_cap_soc_clocks(loaded_bb, max_clocks);
        }
 
        loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
        loaded_ip->max_num_dpp = pool->base.pipe_count;
-       patch_bounding_box(dc, loaded_bb);
+       dcn20_patch_bounding_box(dc, loaded_bb);
 
        return true;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index dccfe07832e31555b0876645cf9241aab2d1d754..fef473d68a4ae5dc893c9487410ea99abed1553d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -95,6 +95,12 @@ struct display_stream_compressor *dcn20_dsc_create(
        struct dc_context *ctx, uint32_t inst);
 void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
 
+void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb);
+void dcn20_cap_soc_clocks(
+               struct _vcs_dpi_soc_bounding_box_st *bb,
+               struct pp_smu_nv_clock_table max_clocks);
+void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
+               struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
 struct hubp *dcn20_hubp_create(
        struct dc_context *ctx,
        uint32_t inst);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index f2e21cb9fbd507af4b5337e5af128e39ce9504e8..da43523a7bfe9e5a4ea67098911ea2a5fbe9cd85 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -149,7 +149,6 @@ struct wm_table {
 struct clk_bw_params {
        unsigned int vram_type;
        unsigned int num_channels;
-       unsigned int dispclk_vco_khz;
        struct clk_limit_table clk_table;
        struct wm_table wm_table;
 };
@@ -192,6 +191,7 @@ struct clk_mgr {
        struct dc_clocks clks;
        bool psr_allow_active_cache;
        int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
+       int dentist_vco_freq_khz;
 #ifdef CONFIG_DRM_AMD_DC_DCN2_1
        struct clk_bw_params *bw_params;
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 2e8cd7956a174bfe13edc75b53b72a1c27f1bb7a..a17a77192690710d5e8ac41a78650ae2b8ebfeea 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -225,8 +225,6 @@ struct clk_mgr_internal {
        struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
 
        /*TODO: figure out which of the below fields should be here vs in asic specific portion */
-       int dentist_vco_freq_khz;
-
        /* Cache the status of DFS-bypass feature*/
        bool dfs_bypass_enabled;
        /* True if the DFS-bypass feature is enabled and active. */