struct kvm_vcpu *vcpu = synic_to_vcpu(synic);
        int ret;
 
-       if (!synic->active)
+       if (!synic->active && !host)
                return 1;
 
        trace_kvm_hv_synic_set_msr(vcpu->vcpu_id, msr, data, host);
        return ret;
 }
 
-static int synic_get_msr(struct kvm_vcpu_hv_synic *synic, u32 msr, u64 *pdata)
+static int synic_get_msr(struct kvm_vcpu_hv_synic *synic, u32 msr, u64 *pdata,
+                        bool host)
 {
        int ret;
 
-       if (!synic->active)
+       if (!synic->active && !host)
                return 1;
 
        ret = 0;
        case HV_X64_MSR_TSC_EMULATION_STATUS:
                hv->hv_tsc_emulation_status = data;
                break;
+       case HV_X64_MSR_TIME_REF_COUNT:
+               /* read-only, but still ignore it if host-initiated */
+               if (!host)
+                       return 1;
+               break;
        default:
                vcpu_unimpl(vcpu, "Hyper-V uhandled wrmsr: 0x%x data 0x%llx\n",
                            msr, data);
                return stimer_set_count(vcpu_to_stimer(vcpu, timer_index),
                                        data, host);
        }
+       case HV_X64_MSR_TSC_FREQUENCY:
+       case HV_X64_MSR_APIC_FREQUENCY:
+               /* read-only, but still ignore it if host-initiated */
+               if (!host)
+                       return 1;
+               break;
        default:
                vcpu_unimpl(vcpu, "Hyper-V uhandled wrmsr: 0x%x data 0x%llx\n",
                            msr, data);
        return 0;
 }
 
-static int kvm_hv_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
+static int kvm_hv_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata,
+                         bool host)
 {
        u64 data = 0;
        struct kvm_vcpu_hv *hv = &vcpu->arch.hyperv;
        case HV_X64_MSR_SIMP:
        case HV_X64_MSR_EOM:
        case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
-               return synic_get_msr(vcpu_to_synic(vcpu), msr, pdata);
+               return synic_get_msr(vcpu_to_synic(vcpu), msr, pdata, host);
        case HV_X64_MSR_STIMER0_CONFIG:
        case HV_X64_MSR_STIMER1_CONFIG:
        case HV_X64_MSR_STIMER2_CONFIG:
                return kvm_hv_set_msr(vcpu, msr, data, host);
 }
 
-int kvm_hv_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
+int kvm_hv_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
 {
        if (kvm_hv_msr_partition_wide(msr)) {
                int r;
                mutex_unlock(&vcpu->kvm->arch.hyperv.hv_lock);
                return r;
        } else
-               return kvm_hv_get_msr(vcpu, msr, pdata);
+               return kvm_hv_get_msr(vcpu, msr, pdata, host);
 }
 
 static __always_inline int get_sparse_bank_no(u64 valid_bank_mask, int bank_no)
 
                vcpu->arch.mcg_status = data;
                break;
        case MSR_IA32_MCG_CTL:
-               if (!(mcg_cap & MCG_CTL_P))
+               if (!(mcg_cap & MCG_CTL_P) &&
+                   (data || !msr_info->host_initiated))
                        return 1;
                if (data != 0 && data != ~(u64)0)
-                       return -1;
+                       return 1;
                vcpu->arch.mcg_ctl = data;
                break;
        default:
 }
 EXPORT_SYMBOL_GPL(kvm_get_msr);
 
-static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
+static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
 {
        u64 data;
        u64 mcg_cap = vcpu->arch.mcg_cap;
                data = vcpu->arch.mcg_cap;
                break;
        case MSR_IA32_MCG_CTL:
-               if (!(mcg_cap & MCG_CTL_P))
+               if (!(mcg_cap & MCG_CTL_P) && !host)
                        return 1;
                data = vcpu->arch.mcg_ctl;
                break;
        case MSR_IA32_MCG_CTL:
        case MSR_IA32_MCG_STATUS:
        case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
-               return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
+               return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
+                                  msr_info->host_initiated);
        case MSR_K7_CLK_CTL:
                /*
                 * Provide expected ramp-up count for K7. All other
        case HV_X64_MSR_TSC_EMULATION_CONTROL:
        case HV_X64_MSR_TSC_EMULATION_STATUS:
                return kvm_hv_get_msr_common(vcpu,
-                                            msr_info->index, &msr_info->data);
+                                            msr_info->index, &msr_info->data,
+                                            msr_info->host_initiated);
                break;
        case MSR_IA32_BBL_CR_CTL3:
                /* This legacy MSR exists but isn't fully documented in current