drm/amdgpu: Normalize reg offsets on JPEG v4.0.3

On VFs and SOCs with GC 9.4.4, VCN RRMT is disabled.
Only local register offsets should be used on JPEG v4.0.3 as they cannot
handle remote access to other AIDs. Since only local offsets are used,
the special write to MCM_ADDR register is no longer needed.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 6ae5a784e18746e207ba51c5da7cb402ded49b1e..a4ebceaaa09cdd313980fa2159d5958522a9db84 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -59,6 +59,12 @@ static int amdgpu_ih_srcid_jpeg[] = {
        VCN_4_0__SRCID__JPEG7_DECODE
 };
 
+static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
+{
+       return amdgpu_sriov_vf(adev) ||
+              (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4));
+}
+
 /**
  * jpeg_v4_0_3_early_init - set function pointers
  *
@@ -734,32 +740,20 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
                0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
        amdgpu_ring_write(ring, 0);
 
-       if (ring->adev->jpeg.inst[ring->me].aid_id) {
-               amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
-                       0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x4);
-       } else {
-               amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
-               amdgpu_ring_write(ring, 0);
-       }
+       amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+       amdgpu_ring_write(ring, 0);
 
        amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
                0, 0, PACKETJ_TYPE0));
        amdgpu_ring_write(ring, 0x3fbc);
 
-       if (ring->adev->jpeg.inst[ring->me].aid_id) {
-               amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET,
-                       0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0));
-               amdgpu_ring_write(ring, 0x0);
-       } else {
-               amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
-               amdgpu_ring_write(ring, 0);
-       }
-
        amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
                0, 0, PACKETJ_TYPE0));
        amdgpu_ring_write(ring, 0x1);
 
+       amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
+       amdgpu_ring_write(ring, 0);
+
        amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
        amdgpu_ring_write(ring, 0);
 }
@@ -834,8 +828,8 @@ void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
 {
        uint32_t reg_offset;
 
-       /* For VF, only local offsets should be used */
-       if (amdgpu_sriov_vf(ring->adev))
+       /* Use normalized offsets if required */
+       if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
                reg = NORMALIZE_JPEG_REG_OFFSET(reg);
 
        reg_offset = (reg << 2);
@@ -881,8 +875,8 @@ void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint
 {
        uint32_t reg_offset;
 
-       /* For VF, only local offsets should be used */
-       if (amdgpu_sriov_vf(ring->adev))
+       /* Use normalized offsets if required */
+       if (jpeg_v4_0_3_normalizn_reqd(ring->adev))
                reg = NORMALIZE_JPEG_REG_OFFSET(reg);
 
        reg_offset = (reg << 2);