mlxsw: reg: Extract flood-mode specific part of mlxsw_reg_sfmr_pack()

In CFF mode, it is necessary to set a different set of SFMR fields. Leave
in mlxsw_reg_sfmr_pack() only the common bits, and move the parts relevant
to controlled flood mode directly to the call site.

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/6f29639ebc3ca0722272e6c644ca910096469413.1700503644.git.petrm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index e8f7a4741bd3f1f9706f31042563f8893a996a32..bd709f7fcae18e4c0ea1e902689a3fbbb24d9ed6 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -1965,16 +1965,11 @@ MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
 
 static inline void mlxsw_reg_sfmr_pack(char *payload,
                                       enum mlxsw_reg_sfmr_op op, u16 fid,
-                                      u16 fid_offset, bool flood_rsp,
-                                      enum mlxsw_reg_bridge_type bridge_type,
                                       bool smpe_valid, u16 smpe)
 {
        MLXSW_REG_ZERO(sfmr, payload);
        mlxsw_reg_sfmr_op_set(payload, op);
        mlxsw_reg_sfmr_fid_set(payload, fid);
-       mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
-       mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp);
-       mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type);
        mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid);
        mlxsw_reg_sfmr_smpe_set(payload, smpe);
 }

diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c
index e954b8cd2ee83443edf746a06d9fcd96160e1525..6a509913bdc7228efc360a7a7d567877d4d73d64 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c
@@ -433,9 +433,12 @@ static int mlxsw_sp_fid_op(const struct mlxsw_sp_fid *fid, bool valid)
        smpe = fid->fid_family->smpe_index_valid ? fid->fid_index : 0;
 
        mlxsw_reg_sfmr_pack(sfmr_pl, mlxsw_sp_sfmr_op(valid), fid->fid_index,
-                           fid->fid_offset, fid->fid_family->flood_rsp,
-                           fid->fid_family->bridge_type,
                            fid->fid_family->smpe_index_valid, smpe);
+       mlxsw_reg_sfmr_fid_offset_set(sfmr_pl, fid->fid_offset);
+       mlxsw_reg_sfmr_flood_rsp_set(sfmr_pl, fid->fid_family->flood_rsp);
+       mlxsw_reg_sfmr_flood_bridge_type_set(sfmr_pl,
+                                            fid->fid_family->bridge_type);
+
        return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
 }
 
@@ -449,10 +452,12 @@ static int mlxsw_sp_fid_edit_op(const struct mlxsw_sp_fid *fid,
        smpe = fid->fid_family->smpe_index_valid ? fid->fid_index : 0;
 
        mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID,
-                           fid->fid_index, fid->fid_offset,
-                           fid->fid_family->flood_rsp,
-                           fid->fid_family->bridge_type,
+                           fid->fid_index,
                            fid->fid_family->smpe_index_valid, smpe);
+       mlxsw_reg_sfmr_fid_offset_set(sfmr_pl, fid->fid_offset);
+       mlxsw_reg_sfmr_flood_rsp_set(sfmr_pl, fid->fid_family->flood_rsp);
+       mlxsw_reg_sfmr_flood_bridge_type_set(sfmr_pl,
+                                            fid->fid_family->bridge_type);
        mlxsw_reg_sfmr_vv_set(sfmr_pl, fid->vni_valid);
        mlxsw_reg_sfmr_vni_set(sfmr_pl, be32_to_cpu(fid->vni));
        mlxsw_reg_sfmr_vtfp_set(sfmr_pl, fid->nve_flood_index_valid);