drm/amdgpu: update default timeout of Aldebaran SQ watchdog

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reivewed-by: Hawking Zhang <hawking.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e39d81b68169338a3d2e9387888f3bb79a319c1b..4df473e3d8e12daf4b747a5a63f5171c5ae7b33d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -177,7 +177,7 @@ uint amdgpu_ras_mask = 0xffffffff;
 int amdgpu_bad_page_threshold = 100;
 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
        .timeout_fatal_disable = false,
-       .period = 0x3f, /* about 8s */
+       .period = 0x23, /* default to max. timeout = 1 << 0x23 cycles */
 };
 
 /**
@@ -545,7 +545,7 @@ module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_di
  * DOC: timeout_period (uint)
  * Modify the watchdog timeout max_cycles as (1 << period)
  */
-MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0x1F = default), timeout maxCycles = (1 << period)");
+MODULE_PARM_DESC(timeout_period, "watchdog timeout period (1 to 0x23(default), timeout maxCycles = (1 << period)");
 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
 
 /**

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index 1faeae14ead90a6667d0db04fafbcf15e43a0110..44024ab9357716431e745c8f3e1bb05a2d87167c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -1138,6 +1138,13 @@ void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
        data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
                             amdgpu_watchdog_timer.timeout_fatal_disable ? 1 :
                                                                           0);
+
+       if (amdgpu_watchdog_timer.timeout_fatal_disable &&
+           (amdgpu_watchdog_timer.period < 1 ||
+            amdgpu_watchdog_timer.period > 0x23)) {
+               dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
+               amdgpu_watchdog_timer.period = 0x23;
+       }
        data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
                             amdgpu_watchdog_timer.period);