/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 #define OMAP24XX_ST_GPIOS_SHIFT                                2
 #define OMAP24XX_ST_GPIOS_MASK                         (1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT                      1
+#define OMAP24XX_ST_32KSYNC_MASK                       (1 << 1)
 #define OMAP24XX_ST_GPT1_SHIFT                         0
 #define OMAP24XX_ST_GPT1_MASK                          (1 << 0)
 
 #define OMAP3430_ST_SR1_MASK                           (1 << 6)
 #define OMAP3430_ST_GPIO1_SHIFT                                3
 #define OMAP3430_ST_GPIO1_MASK                         (1 << 3)
+#define OMAP3430_ST_32KSYNC_SHIFT                      2
+#define OMAP3430_ST_32KSYNC_MASK                       (1 << 2)
 #define OMAP3430_ST_GPT12_SHIFT                                1
 #define OMAP3430_ST_GPT12_MASK                         (1 << 1)
 #define OMAP3430_ST_GPT1_SHIFT                         0