drm/amdgpu: use direct loading on renoir vcn for the moment

PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use
direct loading for the moment till the issue is addressed.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7a6beb2e7c4e8aede558f98f9a3b37aff0affc7a..0c7ac0096a7e619f86abfaedb6b2b8c2395de717 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -100,7 +100,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
        case CHIP_NAVI14:
                fw_name = FIRMWARE_NAVI14;
                if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
-                   (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+                   (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) &&
+                   adev->asic_type != CHIP_RENOIR) /* to be removed while vcn psp loading works */
                        adev->vcn.indirect_sram = true;
                break;
        case CHIP_NAVI12:
@@ -160,7 +161,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
        }
 
        bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
-       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
+           adev->asic_type == CHIP_RENOIR)
                bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 
        for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
@@ -271,7 +273,8 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
                        unsigned offset;
 
                        hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-                       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+                       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
+                           adev->asic_type == CHIP_RENOIR) {
                                offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
                                memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
                                            le32_to_cpu(hdr->ucode_size_bytes));

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 36ad0c0e8efbcb714fd0acc3ed3e261bbf0ab51b..9a076f99bc0fc088d1011f5f939a4d6b30cee3f3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -142,7 +142,8 @@ static int vcn_v2_0_sw_init(void *handle)
        if (r)
                return r;
 
-       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+           adev->asic_type != CHIP_RENOIR) {
                const struct common_firmware_header *hdr;
                hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
                adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
@@ -366,7 +367,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
        uint32_t offset;
 
        /* cache window 0: fw */
-       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+           adev->asic_type != CHIP_RENOIR) {
                WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
                        (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
                WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -411,7 +413,8 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
        uint32_t offset;
 
        /* cache window 0: fw */
-       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+           adev->asic_type != CHIP_RENOIR) {
                if (!indirect) {
                        WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
                                UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),