struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
        unsigned long flags;
        u16 lcladv, rmtadv;
-       u32 intdata;
 
        /* clear interrupt status */
        smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
-       intdata = 0xFFFFFFFF;
-       smsc95xx_write_reg(dev, INT_STS, intdata);
+       smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
 
        mii_check_media(mii, 1, 1);
        mii_ethtool_gset(&dev->mii, &ecmd);
 {
        struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
        unsigned long flags;
-       u32 reg_val;
 
        /* Enable Tx at MAC */
        spin_lock_irqsave(&pdata->mac_cr_lock, flags);
        smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
 
        /* Enable Tx at SCSRs */
-       reg_val = TX_CFG_ON_;
-       smsc95xx_write_reg(dev, TX_CFG, reg_val);
+       smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
 }
 
 /* Starts the Receive path */
 
        netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
 
-       write_buf = HW_CFG_LRST_;
-       ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
+       ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
        if (ret < 0) {
                netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n",
                            ret);
                return ret;
        }
 
-       write_buf = PM_CTL_PHY_RST_;
-       ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
+       ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
        if (ret < 0) {
                netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret);
                return ret;
                  "Read Value from BURST_CAP after writing: 0x%08x\n",
                  read_buf);
 
-       read_buf = DEFAULT_BULK_IN_DELAY;
-       ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
+       ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
        if (ret < 0) {
                netdev_warn(dev->net, "ret = %d\n", ret);
                return ret;
        netif_dbg(dev, ifup, dev->net,
                  "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
 
-       write_buf = 0xFFFFFFFF;
-       ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
+       ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
        if (ret < 0) {
                netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n",
                            ret);
        }
 
        /* Init Tx */
-       write_buf = 0;
-       ret = smsc95xx_write_reg(dev, FLOW, write_buf);
+       ret = smsc95xx_write_reg(dev, FLOW, 0);
        if (ret < 0) {
                netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
                return ret;
        }
 
-       read_buf = AFC_CFG_DEFAULT;
-       ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
+       ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
        if (ret < 0) {
                netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret);
                return ret;
 
        /* Init Rx */
        /* Set Vlan */
-       write_buf = (u32)ETH_P_8021Q;
-       ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
+       ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
        if (ret < 0) {
                netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret);
                return ret;