drm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACTION_SHIFT

No functional changes. Only change the macro from
"DPLL_CFGCR0_DC0_FRAC_SHIFT to DPLL_CFGCR0_DCO_FRACTION_SHIFT
to be consistent with DPLL_CFGCR0_DCO_FRACTION_MASK
and DPLL_CFGCR0_DCO_FRACTION

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1505413899-30876-1-git-send-email-manasi.d.navare@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0befefec73270df70c6c8dc7e9adc97380af7abb..94b40a469afd31fa0c8b2bd6051c683b67554445 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8599,7 +8599,7 @@ enum skl_power_gate {
 #define  DPLL_CFGCR0_LINK_RATE_3240    (6 << 25)
 #define  DPLL_CFGCR0_LINK_RATE_4050    (7 << 25)
 #define  DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
-#define  DPLL_CFGCR0_DCO_FRAC_SHIFT    (10)
+#define  DPLL_CFGCR0_DCO_FRACTION_SHIFT        (10)
 #define  DPLL_CFGCR0_DCO_FRACTION(x)   ((x) << 10)
 #define  DPLL_CFGCR0_DCO_INTEGER_MASK  (0x3ff)
 #define CNL_DPLL_CFGCR0(pll)           _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1da3bb2cc4b464906239dd24f132810906bedbd6..31d14587ad865c44010a29b1a5d2a0c2d99842b3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1212,7 +1212,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
        dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
 
        dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
-                     DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
+                     DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
 
        return dco_freq / (p0 * p1 * p2 * 5);
 }