int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
         u16 data_offset;
        u8 frev, crev;
+       u8 *power_state_offset;
 
        if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
                                   &frev, &crev, &data_offset))
                                       state_array->ucNumEntries, GFP_KERNEL);
        if (!rdev->pm.power_state)
                return state_index;
+       power_state_offset = (u8 *)state_array->states;
        for (i = 0; i < state_array->ucNumEntries; i++) {
                mode_index = 0;
-               power_state = (union pplib_power_state *)&state_array->states[i];
-               /* XXX this might be an inagua bug... */
-               non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
+               power_state = (union pplib_power_state *)power_state_offset;
+               non_clock_array_index = power_state->v2.nonClockInfoIndex;
                non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
                        &non_clock_info_array->nonClockInfo[non_clock_array_index];
                rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
                if (power_state->v2.ucNumDPMLevels) {
                        for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
                                clock_array_index = power_state->v2.clockInfoIndex[j];
-                               /* XXX this might be an inagua bug... */
-                               if (clock_array_index >= clock_info_array->ucNumEntries)
-                                       continue;
                                clock_info = (union pplib_clock_info *)
                                        &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
                                valid = radeon_atombios_parse_pplib_clock_info(rdev,
                                                                   non_clock_info);
                        state_index++;
                }
+               power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
        }
        /* if multiple clock modes, mark the lowest as no display */
        for (i = 0; i < state_index; i++) {