* used by the Port
         */
        u8 mps_bg_map[MAX_NPORTS];      /* MPS Buffer Group Map */
+       bool write_w_imm_support;       /* FW supports WRITE_WITH_IMMEDIATE */
 };
 
 /* State needed to monitor the forward progress of SGE Ingress DMA activities
 
                         "max_ordird_qp %d max_ird_adapter %d\n",
                         adap->params.max_ordird_qp,
                         adap->params.max_ird_adapter);
+
+               /* Enable write_with_immediate if FW supports it */
+               params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
+               ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
+                                     val);
+               adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
                adap->num_ofld_uld += 2;
        }
        if (caps_cmd.iscsicaps) {
 
        lld->ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
        lld->nodeid = dev_to_node(adap->pdev_dev);
        lld->fr_nsmr_tpte_wr_support = adap->params.fr_nsmr_tpte_wr_support;
+       lld->write_w_imm_support = adap->params.write_w_imm_support;
 }
 
 static void uld_attach(struct adapter *adap, unsigned int uld)
 
        void **iscsi_ppm;                    /* iscsi page pod manager */
        int nodeid;                          /* device numa node id */
        bool fr_nsmr_tpte_wr_support;        /* FW supports FR_NSMR_TPTE_WR */
+       bool write_w_imm_support;         /* FW supports WRITE_WITH_IMMEDIATE */
 };
 
 struct cxgb4_uld_info {
 
        FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
        FW_PARAMS_PARAM_DEV_MPSBGMAP    = 0x1E,
        FW_PARAMS_PARAM_DEV_HMA_SIZE    = 0x20,
+       FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
 };
 
 /*