arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers

Enable the PCIe controller and PHY nodes corresponding to RDP 433.

Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
index 1bb8d96c9a8270f3ff3366812e34f5ee7eb44d6c..165ebbb59511918ec18991bbc563ed9f4db1c84b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -8,6 +8,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "ipq9574-rdp-common.dtsi"
 
 / {
@@ -15,6 +16,45 @@
        compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
 };
 
+&pcie1_phy {
+       status = "okay";
+};
+
+&pcie1 {
+       pinctrl-0 = <&pcie1_default>;
+       pinctrl-names = "default";
+
+       perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&pcie2_phy {
+       status = "okay";
+};
+
+&pcie2 {
+       pinctrl-0 = <&pcie2_default>;
+       pinctrl-names = "default";
+
+       perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&pcie3_phy {
+       status = "okay";
+};
+
+&pcie3 {
+       pinctrl-0 = <&pcie3_default>;
+       pinctrl-names = "default";
+
+       perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
 &sdhc_1 {
        pinctrl-0 = <&sdc_default_state>;
        pinctrl-names = "default";
@@ -28,6 +68,79 @@
 };
 
 &tlmm {
+
+       pcie1_default: pcie1-default-state {
+               clkreq-n-pins {
+                       pins = "gpio25";
+                       function = "pcie1_clk";
+                       drive-strength = <6>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio26";
+                       function = "gpio";
+                       drive-strength = <8>;
+                       bias-pull-down;
+                       output-low;
+               };
+
+               wake-n-pins {
+                       pins = "gpio27";
+                       function = "pcie1_wake";
+                       drive-strength = <6>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie2_default: pcie2-default-state {
+               clkreq-n-pins {
+                       pins = "gpio28";
+                       function = "pcie2_clk";
+                       drive-strength = <6>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio29";
+                       function = "gpio";
+                       drive-strength = <8>;
+                       bias-pull-down;
+                       output-low;
+               };
+
+               wake-n-pins {
+                       pins = "gpio30";
+                       function = "pcie2_wake";
+                       drive-strength = <6>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie3_default: pcie3-default-state {
+               clkreq-n-pins {
+                       pins = "gpio31";
+                       function = "pcie3_clk";
+                       drive-strength = <6>;
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio32";
+                       function = "gpio";
+                       drive-strength = <8>;
+                       bias-pull-up;
+                       output-low;
+               };
+
+               wake-n-pins {
+                       pins = "gpio33";
+                       function = "pcie3_wake";
+                       drive-strength = <6>;
+                       bias-pull-up;
+               };
+       };
+
        sdc_default_state: sdc-default-state {
                clk-pins {
                        pins = "gpio5";