drm/amd/powerplay: add more members for dpm table

These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 05c8b44e0632225e3e72520389b2ce2f4bc285f0..c6832be8356f42461ef1b0c7695cdb7cc477f1d2 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -48,6 +48,7 @@
 
 #define SMU11_TOOL_SIZE                        0x19000
 
+#define MAX_DPM_LEVELS 16
 #define MAX_PCIE_CONF 2
 
 #define CLK_MAP(clk, index) \
@@ -91,9 +92,17 @@ struct smu_11_0_max_sustainable_clocks {
        uint32_t soc_clock;
 };
 
+struct smu_11_0_dpm_clk_level {
+       bool                            enabled;
+       uint32_t                        value;
+};
+
 struct smu_11_0_dpm_table {
-       uint32_t    min;        /* MHz */
-       uint32_t    max;        /* MHz */
+       uint32_t                        min;        /* MHz */
+       uint32_t                        max;        /* MHz */
+       uint32_t                        count;
+       bool                            is_fine_grained;
+       struct smu_11_0_dpm_clk_level   dpm_levels[MAX_DPM_LEVELS];
 };
 
 struct smu_11_0_pcie_table {
@@ -107,7 +116,9 @@ struct smu_11_0_dpm_tables {
        struct smu_11_0_dpm_table        uclk_table;
        struct smu_11_0_dpm_table        eclk_table;
        struct smu_11_0_dpm_table        vclk_table;
+       struct smu_11_0_dpm_table        vclk1_table;
        struct smu_11_0_dpm_table        dclk_table;
+       struct smu_11_0_dpm_table        dclk1_table;
        struct smu_11_0_dpm_table        dcef_table;
        struct smu_11_0_dpm_table        pixel_table;
        struct smu_11_0_dpm_table        display_table;