assert_pch_transcoder_disabled(dev_priv, pipe);
 
        /* For PCH output, training FDI link */
-       dev_priv->display.fdi_link_train(crtc, crtc_state);
+       intel_fdi_link_train(crtc, crtc_state);
 
        /* We need to program the right clock selection before writing the pixel
         * mutliplier into the DPLL. */
 
 #include "intel_fdi.h"
 #include "intel_sideband.h"
 
+void intel_fdi_link_train(struct intel_crtc *crtc,
+                         const struct intel_crtc_state *crtc_state)
+{
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+       dev_priv->display.fdi_link_train(crtc, crtc_state);
+}
+
 /* units of 100MHz */
 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
 {
 
 void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
 void lpt_fdi_program_mphy(struct drm_i915_private *i915);
 
+void intel_fdi_link_train(struct intel_crtc *crtc,
+                         const struct intel_crtc_state *crtc_state);
 #endif