INTEL_I945G_IDS(&gen3_early_ops),
INTEL_I945GM_IDS(&gen3_early_ops),
INTEL_VLV_IDS(&gen6_early_ops),
- INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
- INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
+ INTEL_PNV_IDS(&gen3_early_ops),
INTEL_I965G_IDS(&gen3_early_ops),
INTEL_G33_IDS(&gen3_early_ops),
INTEL_I965GM_IDS(&gen3_early_ops),
INTEL_I965GM_IDS(&i965gm_display),
INTEL_GM45_IDS(&gm45_display),
INTEL_G45_IDS(&g45_display),
- INTEL_PINEVIEW_G_IDS(&pnv_display),
- INTEL_PINEVIEW_M_IDS(&pnv_display),
+ INTEL_PNV_IDS(&pnv_display),
INTEL_IRONLAKE_D_IDS(&ilk_d_display),
INTEL_IRONLAKE_M_IDS(&ilk_m_display),
INTEL_SNB_D_IDS(&snb_display),
INTEL_I965GM_IDS(&i965gm_info),
INTEL_GM45_IDS(&gm45_info),
INTEL_G45_IDS(&g45_info),
- INTEL_PINEVIEW_G_IDS(&pnv_g_info),
- INTEL_PINEVIEW_M_IDS(&pnv_m_info),
+ INTEL_PNV_G_IDS(&pnv_g_info),
+ INTEL_PNV_M_IDS(&pnv_m_info),
INTEL_IRONLAKE_D_IDS(&ilk_d_info),
INTEL_IRONLAKE_M_IDS(&ilk_m_info),
INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
-#define INTEL_PINEVIEW_G_IDS(info) \
+#define INTEL_PNV_G_IDS(info) \
INTEL_VGA_DEVICE(0xa001, info)
-#define INTEL_PINEVIEW_M_IDS(info) \
+#define INTEL_PNV_M_IDS(info) \
INTEL_VGA_DEVICE(0xa011, info)
+#define INTEL_PNV_IDS(info) \
+ INTEL_PNV_G_IDS(info), \
+ INTEL_PNV_M_IDS(info)
+
#define INTEL_IRONLAKE_D_IDS(info) \
INTEL_VGA_DEVICE(0x0042, info)