drm/i915: Pass intel_crtc to update_wm functions

Unify our approach to things by passing around intel_crtc instead of
drm_crtc.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1477946245-14134-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea1cfc6499615bab0e4720c634c4b0622caa8d7c..98f59863fe6b392e4bf49872782e3f36f872663e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -503,7 +503,7 @@ struct drm_i915_display_funcs {
        void (*initial_watermarks)(struct intel_crtc_state *cstate);
        void (*optimize_watermarks)(struct intel_crtc_state *cstate);
        int (*compute_global_watermarks)(struct drm_atomic_state *state);
-       void (*update_wm)(struct drm_crtc *crtc);
+       void (*update_wm)(struct intel_crtc *crtc);
        int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
        void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
        /* Returns the active state of the crtc, and if the crtc is active,

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 00784d950d51caa36ff8304ce0e00e0aed37fb36..936870d18851ab2a66131c53ebfd864607b3ed79 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5073,7 +5073,7 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
        crtc->wm.cxsr_allowed = true;
 
        if (pipe_config->update_wm_post && pipe_config->base.active)
-               intel_update_watermarks(&crtc->base);
+               intel_update_watermarks(crtc);
 
        if (old_pri_state) {
                struct intel_plane_state *primary_state =
@@ -5171,7 +5171,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
        if (dev_priv->display.initial_watermarks != NULL)
                dev_priv->display.initial_watermarks(pipe_config);
        else if (pipe_config->update_wm_pre)
-               intel_update_watermarks(&crtc->base);
+               intel_update_watermarks(crtc);
 }
 
 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
@@ -5491,7 +5491,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
        if (dev_priv->display.initial_watermarks != NULL)
                dev_priv->display.initial_watermarks(pipe_config);
        else
-               intel_update_watermarks(crtc);
+               intel_update_watermarks(intel_crtc);
 
        /* XXX: Do the pipe assertions at the right place for BXT DSI. */
        if (!transcoder_is_dsi(cpu_transcoder))
@@ -6744,7 +6744,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
        intel_color_load_luts(&pipe_config->base);
 
-       intel_update_watermarks(crtc);
+       intel_update_watermarks(intel_crtc);
        intel_enable_pipe(intel_crtc);
 
        assert_vblank_disabled(crtc);
@@ -6797,7 +6797,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 
        intel_color_load_luts(&pipe_config->base);
 
-       intel_update_watermarks(crtc);
+       intel_update_watermarks(intel_crtc);
        intel_enable_pipe(intel_crtc);
 
        assert_vblank_disabled(crtc);
@@ -6913,7 +6913,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
                encoder->base.crtc = NULL;
 
        intel_fbc_disable(intel_crtc);
-       intel_update_watermarks(crtc);
+       intel_update_watermarks(intel_crtc);
        intel_disable_shared_dpll(intel_crtc);
 
        domains = intel_crtc->enabled_power_domains;
@@ -14397,7 +14397,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
                        intel_check_pch_fifo_underruns(dev_priv);
 
                        if (!crtc->state->active)
-                               intel_update_watermarks(crtc);
+                               intel_update_watermarks(intel_crtc);
                }
        }
 

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 67b90527217c44b5fedb6713f96e28b6e1390225..8ae13a6d0cc351b9a546fe029cdb36038409bf53 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1709,7 +1709,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 void intel_init_clock_gating(struct drm_device *dev);
 void intel_suspend_hw(struct drm_device *dev);
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct drm_crtc *crtc);
+void intel_update_watermarks(struct intel_crtc *crtc);
 void intel_init_pm(struct drm_device *dev);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_device *dev);

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 419c5eb88d7cbbeb48e024fe139a28f3be07ef5f..9bcb15a74a8333b5dfd656b993122985e765cb9b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -640,9 +640,9 @@ static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
        return enabled;
 }
 
-static void pineview_update_wm(struct drm_crtc *unused_crtc)
+static void pineview_update_wm(struct intel_crtc *unused_crtc)
 {
-       struct drm_device *dev = unused_crtc->dev;
+       struct drm_device *dev = unused_crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_crtc *crtc;
        const struct cxsr_latency *latency;
@@ -1330,20 +1330,19 @@ static void vlv_merge_wm(struct drm_device *dev,
        }
 }
 
-static void vlv_update_wm(struct drm_crtc *crtc)
+static void vlv_update_wm(struct intel_crtc *crtc)
 {
-       struct drm_device *dev = crtc->dev;
+       struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       enum pipe pipe = intel_crtc->pipe;
+       enum pipe pipe = crtc->pipe;
        struct vlv_wm_values wm = {};
 
-       vlv_compute_wm(intel_crtc);
+       vlv_compute_wm(crtc);
        vlv_merge_wm(dev, &wm);
 
        if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
                /* FIXME should be part of crtc atomic commit */
-               vlv_pipe_set_fifo_size(intel_crtc);
+               vlv_pipe_set_fifo_size(crtc);
                return;
        }
 
@@ -1359,9 +1358,9 @@ static void vlv_update_wm(struct drm_crtc *crtc)
                intel_set_memory_cxsr(dev_priv, false);
 
        /* FIXME should be part of crtc atomic commit */
-       vlv_pipe_set_fifo_size(intel_crtc);
+       vlv_pipe_set_fifo_size(crtc);
 
-       vlv_write_wm_values(intel_crtc, &wm);
+       vlv_write_wm_values(crtc, &wm);
 
        DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
                      "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
@@ -1385,9 +1384,9 @@ static void vlv_update_wm(struct drm_crtc *crtc)
 
 #define single_plane_enabled(mask) is_power_of_2(mask)
 
-static void g4x_update_wm(struct drm_crtc *crtc)
+static void g4x_update_wm(struct intel_crtc *crtc)
 {
-       struct drm_device *dev = crtc->dev;
+       struct drm_device *dev = crtc->base.dev;
        static const int sr_latency_ns = 12000;
        struct drm_i915_private *dev_priv = to_i915(dev);
        int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
@@ -1443,9 +1442,9 @@ static void g4x_update_wm(struct drm_crtc *crtc)
                intel_set_memory_cxsr(dev_priv, true);
 }
 
-static void i965_update_wm(struct drm_crtc *unused_crtc)
+static void i965_update_wm(struct intel_crtc *unused_crtc)
 {
-       struct drm_device *dev = unused_crtc->dev;
+       struct drm_device *dev = unused_crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_crtc *crtc;
        int srwm = 1;
@@ -1517,9 +1516,9 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
 
 #undef FW_WM
 
-static void i9xx_update_wm(struct drm_crtc *unused_crtc)
+static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 {
-       struct drm_device *dev = unused_crtc->dev;
+       struct drm_device *dev = unused_crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        const struct intel_watermark_params *wm_info;
        uint32_t fwater_lo;
@@ -1650,9 +1649,9 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
                intel_set_memory_cxsr(dev_priv, true);
 }
 
-static void i845_update_wm(struct drm_crtc *unused_crtc)
+static void i845_update_wm(struct intel_crtc *unused_crtc)
 {
-       struct drm_device *dev = unused_crtc->dev;
+       struct drm_device *dev = unused_crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct drm_crtc *crtc;
        const struct drm_display_mode *adjusted_mode;
@@ -4193,18 +4192,17 @@ skl_compute_wm(struct drm_atomic_state *state)
        return 0;
 }
 
-static void skl_update_wm(struct drm_crtc *crtc)
+static void skl_update_wm(struct intel_crtc *intel_crtc)
 {
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       struct drm_device *dev = crtc->dev;
+       struct drm_device *dev = intel_crtc->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct skl_wm_values *results = &dev_priv->wm.skl_results;
        struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
-       struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+       struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
        struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
        enum pipe pipe = intel_crtc->pipe;
 
-       if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
+       if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
                return;
 
        mutex_lock(&dev_priv->wm.wm_mutex);
@@ -4215,7 +4213,7 @@ static void skl_update_wm(struct drm_crtc *crtc)
         * the pipe's shut off, just do so here. Already active pipes will have
         * their watermarks updated once we update their planes.
         */
-       if (crtc->state->active_changed) {
+       if (intel_crtc->base.state->active_changed) {
                int plane;
 
                for_each_universal_plane(dev_priv, pipe, plane)
@@ -4654,9 +4652,9 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
  * We don't use the sprite, so we can ignore that.  And on Crestline we have
  * to set the non-SR watermarks to 8.
  */
-void intel_update_watermarks(struct drm_crtc *crtc)
+void intel_update_watermarks(struct intel_crtc *crtc)
 {
-       struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
        if (dev_priv->display.update_wm)
                dev_priv->display.update_wm(crtc);