*/
int flash_real_protect(flash_info_t *info, long sector, int prot)
{
- long sectnum;
ulong start;
-
- for(sectnum = 0; sectnum<info->sector_count; sectnum++)
- if(info->start[sectnum] == sector)
- break;
-
- flash_write_cmd(info, sectnum, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sectnum, 0, FLASH_CMD_PROTECT);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
if(prot)
- flash_write_cmd(info, sectnum, 0, FLASH_CMD_PROTECT_SET);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
else
- flash_write_cmd(info, sectnum, 0, FLASH_CMD_PROTECT_CLEAR);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
/* Wait for command completion */
start = get_timer (0);
- while(!flash_isset(info, sectnum, 0, FLASH_STATUS_DONE)) {
+ while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %sprotect timeout at address %lx\n", prot?"":"un", sector);
- flash_write_cmd(info, sectnum, 0, FLASH_CMD_RESET);
+ printf("Flash %sprotect timeout at address %lx\n", prot?"":"un", info->start[sector]);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
return 1;
}
}
- if(!flash_isequal(info,sectnum, 0, FLASH_STATUS_DONE)) {
- printf("\nFlash %sprotect error at address %lx\n", prot?"":"un",sector);
+ if(!flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+ printf("\nFlash %sprotect error at address %lx\n", prot?"":"un",info->start[sector]);
flash_status_display(info, 0);
- flash_write_cmd(info, sectnum, 0, FLASH_CMD_RESET);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
return 1;
}
- flash_write_cmd(info, sectnum, 0, FLASH_CMD_RESET);
- info->protect[sectnum] = prot;
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ info->protect[sector] = prot;
/* Intel's unprotect unprotects all locking */
if(prot == 0) {
int i;
for(i = 0 ; i<info->sector_count; i++) {
if(info->protect[i])
- flash_real_protect(info, info->start[i], 1);
+ flash_real_protect(info, i, 1);
}
}
* - Address Multiplexing where A5 is output on A14 pin
* (A6 on A15, and so on),
* - use address pins A13-A15 as bank select,
- * - A7 is output on SDA10 during an ACTIVATE command,
+ * - A9 is output on SDA10 during an ACTIVATE command,
* - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
* - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
* is 3 clocks,
/*
* With 16MB SDRAM, OR4 is configured as follows
* - 4 internal banks per device
- * - Row start address bit is A7 with LSDMR[PBI] = 0
- * - 13 row address lines
+ * - Row start address bit is A10 with LSDMR[PBI] = 0
+ * - 12 row address lines
* - Back-to-back page mode
* - Internal bank interleaving within save device enabled
*/