u16 pos_x, unsigned long *core_clk);
        unsigned long (*calc_core_clk) (enum omap_channel channel,
                u16 width, u16 height, u16 out_width, u16 out_height);
+       u8 num_fifos;
 };
 
+#define DISPC_MAX_NR_FIFOS 5
+
 static struct {
        struct platform_device *pdev;
        void __iomem    *base;
        int irq;
        struct clk *dss_clk;
 
-       u32     fifo_size[MAX_DSS_OVERLAYS];
+       u32 fifo_size[DISPC_MAX_NR_FIFOS];
+       /* maps which plane is using a fifo. fifo-id -> plane-id */
+       int fifo_assignment[DISPC_MAX_NR_FIFOS];
 
        spinlock_t irq_lock;
        u32 irq_error_mask;
        dispc_write_reg(DISPC_SIZE_MGR(channel), val);
 }
 
-static void dispc_read_plane_fifo_sizes(void)
+static void dispc_init_fifos(void)
 {
        u32 size;
-       int plane;
+       int fifo;
        u8 start, end;
        u32 unit;
 
 
        dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
 
-       for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
-               size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
+       for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
+               size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
                size *= unit;
-               dispc.fifo_size[plane] = size;
+               dispc.fifo_size[fifo] = size;
+
+               /*
+                * By default fifos are mapped directly to overlays, fifo 0 to
+                * ovl 0, fifo 1 to ovl 1, etc.
+                */
+               dispc.fifo_assignment[fifo] = fifo;
        }
 }
 
 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
 {
-       return dispc.fifo_size[plane];
+       int fifo;
+       u32 size = 0;
+
+       for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
+               if (dispc.fifo_assignment[fifo] == plane)
+                       size += dispc.fifo_size[fifo];
+       }
+
+       return size;
 }
 
 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
 
        dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
 
-       dispc_read_plane_fifo_sizes();
+       dispc_init_fifos();
 
        dispc_configure_burst_sizes();
 
        .hp_max                 =       256,
        .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
        .calc_core_clk          =       calc_core_clk_24xx,
+       .num_fifos              =       3,
 };
 
 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
        .hp_max                 =       256,
        .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
        .calc_core_clk          =       calc_core_clk_34xx,
+       .num_fifos              =       3,
 };
 
 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
        .hp_max                 =       4096,
        .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
        .calc_core_clk          =       calc_core_clk_34xx,
+       .num_fifos              =       3,
 };
 
 static const struct dispc_features omap44xx_dispc_feats __initconst = {
        .hp_max                 =       4096,
        .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
        .calc_core_clk          =       calc_core_clk_44xx,
+       .num_fifos              =       5,
 };
 
 static int __init dispc_init_features(struct device *dev)