arm64: dts: qcom: x1e80100: Add PCIe IOMMU

x1e80100 has an SMMUv3 connected to PCIe which is normally controlled by
Gunyah and is thus transparent to the OS. However if we boot Linux in
EL2, without Gunyah, we need to manage this IOMMU ourselves. To make
that easier, and since the hardware actually exists, just not "usually"
managed by Linux, describe it in the dts as "reserved".

Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-4-24e9b4572e15@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 46b79fce92c90d969e3de48bc88e27915d1592bb..7a3e75294be545a719f3543a8b874900f7c78f99 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -7940,6 +7940,20 @@
                        dma-coherent;
                };
 
+               pcie_smmu: iommu@15400000 {
+                       compatible = "arm,smmu-v3";
+                       reg = <0 0x15400000 0 0x80000>;
+                       #iommu-cells = <1>;
+                       interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "eventq",
+                                         "gerror",
+                                         "cmdq-sync";
+                       dma-coherent;
+                       status = "reserved"; /* Controlled by Gunyah. */
+               };
+
                intc: interrupt-controller@17000000 {
                        compatible = "arm,gic-v3";
                        reg = <0 0x17000000 0 0x10000>,     /* GICD */