}
APBState *pci_apb_init(hwaddr special_base,
- hwaddr mem_base,
- PCIBus **busA, PCIBus **busB)
+ hwaddr mem_base)
{
DeviceState *dev;
SysBusDevice *s;
APBState *d;
IOMMUState *is;
PCIDevice *pci_dev;
- PCIBridge *br;
/* Ultrasparc PBM main bus */
dev = qdev_create(NULL, TYPE_APB);
/* APB secondary busses */
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
TYPE_PBM_PCI_BRIDGE);
- br = PCI_BRIDGE(pci_dev);
- pci_bridge_map_irq(br, "pciB", pci_pbm_map_irq);
+ d->bridgeB = PCI_BRIDGE(pci_dev);
+ pci_bridge_map_irq(d->bridgeB, "pciB", pci_pbm_map_irq);
qdev_init_nofail(&pci_dev->qdev);
- *busB = pci_bridge_get_sec_bus(br);
pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
TYPE_PBM_PCI_BRIDGE);
- br = PCI_BRIDGE(pci_dev);
- pci_bridge_map_irq(br, "pciA", pci_pbm_map_irq);
+ d->bridgeA = PCI_BRIDGE(pci_dev);
+ pci_bridge_map_irq(d->bridgeA, "pciA", pci_pbm_map_irq);
qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
qdev_init_nofail(&pci_dev->qdev);
- *busA = pci_bridge_get_sec_bus(br);
return d;
}
#include "cpu.h"
#include "hw/hw.h"
#include "hw/pci/pci.h"
+#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/apb.h"
#include "hw/i386/pc.h"
prom_init(hwdef->prom_addr, bios_name);
- apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, &pci_busA, &pci_busB);
+ apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE);
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
}
pci_bus = PCI_HOST_BRIDGE(apb)->bus;
+ pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
+ pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
/* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
reserved (leaving no slots free after on-board devices) however slots
MemoryRegion pci_ioport;
uint64_t pci_irq_in;
IOMMUState iommu;
+ PCIBridge *bridgeA;
+ PCIBridge *bridgeB;
uint32_t pci_control[16];
uint32_t pci_irq_map[8];
uint32_t pci_err_irq_map[4];
OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
APBState *pci_apb_init(hwaddr special_base,
- hwaddr mem_base,
- PCIBus **bus2, PCIBus **bus3);
+ hwaddr mem_base);
#endif