arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent

The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
mark the APPS and PCIe ones as well.

Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
Fixes: 2dba7a613a6e ("arm64: dts: qcom: sa8775p: add the pcie smmu node")
Cc: stable@vger.kernel.org
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
Rule: add
Link: https://lore.kernel.org/stable/20240723075948.9545-1-quic_qqzhou%40quicinc.com
Link: https://lore.kernel.org/r/20240725072117.22425-1-quic_qqzhou@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index cc4ad901fbac3ba077ba308fc3a50d86daa24560..ad8e567575e5627362f0817951a5371dc585bbbf 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3070,6 +3070,7 @@
                        reg = <0x0 0x15000000 0x0 0x100000>;
                        #iommu-cells = <2>;
                        #global-interrupts = <2>;
+                       dma-coherent;
 
                        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
@@ -3208,6 +3209,7 @@
                        reg = <0x0 0x15200000 0x0 0x80000>;
                        #iommu-cells = <2>;
                        #global-interrupts = <2>;
+                       dma-coherent;
 
                        interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,