{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
 };
 
+static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
+{
+       struct sof_ipc_pm_core_config pm_core_config = {
+               .hdr = {
+                       .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
+                       .size = sizeof(pm_core_config),
+               },
+               .enable_mask = sdev->enabled_cores_mask | BIT(core),
+       };
+
+       /* power up primary core if not already powered up and return */
+       if (core == SOF_DSP_PRIMARY_CORE)
+               return hda_dsp_enable_core(sdev, BIT(core));
+
+       /* notify DSP for secondary cores */
+       return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd,
+                                &pm_core_config, sizeof(pm_core_config),
+                                &pm_core_config, sizeof(pm_core_config));
+}
+
+static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
+{
+       struct sof_ipc_pm_core_config pm_core_config = {
+               .hdr = {
+                       .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
+                       .size = sizeof(pm_core_config),
+               },
+               .enable_mask = sdev->enabled_cores_mask & ~BIT(core),
+       };
+
+       /* power down primary core and return */
+       if (core == SOF_DSP_PRIMARY_CORE)
+               return hda_dsp_core_reset_power_down(sdev, BIT(core));
+
+       /* notify DSP for secondary cores */
+       return sof_ipc_tx_message(sdev->ipc, pm_core_config.hdr.cmd,
+                                &pm_core_config, sizeof(pm_core_config),
+                                &pm_core_config, sizeof(pm_core_config));
+}
+
 /* Tigerlake ops */
 const struct snd_sof_dsp_ops sof_tgl_ops = {
        /* probe/remove/shutdown */
        /* dsp core power up/down */
        .core_power_up = hda_dsp_enable_core,
        .core_power_down = hda_dsp_core_reset_power_down,
+       .core_get = tgl_dsp_core_get,
+       .core_put = tgl_dsp_core_put,
 
        /* firmware run */
        .run = hda_dsp_cl_boot_firmware_iccmax,