x86/bugs: always use x86_spec_ctrl_base or _priv when setting spec ctrl MSR

x86_spec_ctrl_base and x86_spec_ctrl_priv contain reserved bits from the
first read of the spec ctrl MSR but in one case neither of these are
used when updating the MSR in x86_spec_ctrl_set.

This does not seem to cause problems now, but add it in for consistency.
In this case, we need to use x86_spec_ctrl_base because IBRS isn't being
enabled.

Fixes: edcba197bb44 ("x86/bugs/IBRS: Use variable instead of defines for enabling IBRS")
Signed-off-by: Daniel Jordan <daniel.m.jordan@oracle.com>
Reviewed-by: Mihai Carabas <mihai.carabas@oracle.com>
Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
(cherry picked from commit a5429dd0a22342bf3e03649af25e5ad3dd6e01e7)

Orabug: 28271063

Signed-off-by: Anjali Kulkarni <anjali.k.kulkarni@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.duan@oracle.com>
Signed-off-by: Brian Maly <brian.maly@oracle.com>

diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c
index 7024d2908e778f01c1b2246f9f84849035714fe5..fbad062e87c30d111c239cb648df64ad9c5b6ef9 100644 (file)
--- a/arch/x86/kernel/cpu/bugs_64.c
+++ b/arch/x86/kernel/cpu/bugs_64.c
@@ -279,7 +279,8 @@ void x86_spec_ctrl_set(u64 val)
                        if (val & SPEC_CTRL_IBRS)
                                host = this_cpu_read(x86_spec_ctrl_priv_cpu);
                        else
-                               host = val & ~(SPEC_CTRL_SSBD);
+                               host = (x86_spec_ctrl_base | val) &
+                                      ~SPEC_CTRL_SSBD;
                } else {
                        if (ibrs_inuse && (val & SPEC_CTRL_IBRS))
                                host = this_cpu_read(x86_spec_ctrl_priv_cpu);