return 0;
 }
 
+static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int data;
+
+       /* AMD_CG_SUPPORT_SDMA_MGCG */
+       data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
+       if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
+               *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
+
+       /* AMD_CG_SUPPORT_SDMA_LS */
+       data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
+       if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
+               *flags |= AMD_CG_SUPPORT_SDMA_LS;
+}
+
 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
        .name = "sdma_v3_0",
        .early_init = sdma_v3_0_early_init,
        .soft_reset = sdma_v3_0_soft_reset,
        .set_clockgating_state = sdma_v3_0_set_clockgating_state,
        .set_powergating_state = sdma_v3_0_set_powergating_state,
+       .get_clockgating_state = sdma_v3_0_get_clockgating_state,
 };
 
 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {