clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
                        resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
-                                <&gcc 21>;
+                                <&gcc GCC_PCIE_0_PIPE_ARES>;
                        reset-names = "phy", "pipe";
 
                        clock-output-names = "pcie_0_pipe_clk";
                                 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
                        clock-names = "iface", "aux", "master_bus", "slave_bus";
 
-                       resets = <&gcc 18>,
-                                <&gcc 17>,
-                                <&gcc 15>,
-                                <&gcc 19>,
+                       resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
+                                <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
+                                <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
+                                <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
                                 <&gcc GCC_PCIE_0_BCR>,
-                                <&gcc 16>;
+                                <&gcc GCC_PCIE_0_AHB_ARES>;
                        reset-names = "axi_m",
                                      "axi_s",
                                      "axi_m_sticky",