uint64_t dst_addr, uint64_t size);
        int (*fill_mem)(struct amdgpu_device *adev, uint64_t dst_addr,
                        uint32_t data, uint64_t size);
+       void (*update_memory_power_gating)(struct amdgpu_device *adev, bool enable);
 };
 
 int amdgpu_lsdma_copy_mem(struct amdgpu_device *adev, uint64_t src_addr,
 
        return ret;
 }
 
+static void lsdma_v6_0_update_memory_power_gating(struct amdgpu_device *adev,
+                                                bool enable)
+{
+       uint32_t tmp;
+
+       tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);
+       tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);
+       WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
+
+       tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);
+       WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
+}
+
 const struct amdgpu_lsdma_funcs lsdma_v6_0_funcs = {
        .copy_mem = lsdma_v6_0_copy_mem,
-       .fill_mem = lsdma_v6_0_fill_mem
+       .fill_mem = lsdma_v6_0_fill_mem,
+       .update_memory_power_gating = lsdma_v6_0_update_memory_power_gating
 };
 
 static int soc21_common_set_powergating_state(void *handle,
                                           enum amd_powergating_state state)
 {
-       /* TODO */
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+       switch (adev->ip_versions[LSDMA_HWIP][0]) {
+       case IP_VERSION(6, 0, 0):
+               adev->lsdma.funcs->update_memory_power_gating(adev,
+                               state == AMD_PG_STATE_GATE);
+               break;
+       default:
+               break;
+       }
+
        return 0;
 }