For NGBE devices, the queue number is limited to be 1 when SRIOV is
enabled. In this case, IRQ vector[0] is used for MISC and vector[1] is
used for queue, based on the previous patches. But for the hardware
design, the IRQ vector[1] must be allocated for use by the VF[6] when
the number of VFs is 7. So the IRQ vector[0] should be shared for PF
MISC and QUEUE interrupts.
+-----------+----------------------+
| Vector    | Assigned To          |
+-----------+----------------------+
| Vector 0  | PF MISC and QUEUE    |
| Vector 1  | VF 6                 |
| Vector 2  | VF 5                 |
| Vector 3  | VF 4                 |
| Vector 4  | VF 3                 |
| Vector 5  | VF 2                 |
| Vector 6  | VF 1                 |
| Vector 7  | VF 0                 |
+-----------+----------------------+
Minimize code modifications, only adjust the IRQ vector number for this
case.
Fixes: 877253d2cbf2 ("net: ngbe: add sriov function support")
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Larysa Zaremba <larysa.zaremba@intel.com>
Link: https://patch.msgid.link/20250701063030.59340-4-jiawenwu@trustnetic.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
        wx->msix_entry->entry = nvecs;
        wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs);
 
+       if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) {
+               wx->msix_entry->entry = 0;
+               wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0);
+               wx->msix_q_entries[0].entry = 0;
+               wx->msix_q_entries[0].vector = pci_irq_vector(wx->pdev, 1);
+       }
+
        return 0;
 }
 
 
        if (direction == -1) {
                /* other causes */
+               if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags))
+                       msix_vector = 0;
                msix_vector |= WX_PX_IVAR_ALLOC_VAL;
                index = 0;
                ivar = rd32(wx, WX_PX_MISC_IVAR);
 
        wr32m(wx, WX_PSR_VM_CTL, WX_PSR_VM_CTL_POOL_MASK, 0);
        wx->ring_feature[RING_F_VMDQ].offset = 0;
 
+       clear_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags);
        clear_bit(WX_FLAG_SRIOV_ENABLED, wx->flags);
        /* Disable VMDq flag so device will be set in NM mode */
        if (wx->ring_feature[RING_F_VMDQ].limit == 1)
        set_bit(WX_FLAG_SRIOV_ENABLED, wx->flags);
        dev_info(&wx->pdev->dev, "SR-IOV enabled with %d VFs\n", num_vfs);
 
+       if (num_vfs == 7 && wx->mac.type == wx_mac_em)
+               set_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags);
+
        /* Enable VMDq flag so device will be set in VM mode */
        set_bit(WX_FLAG_VMDQ_ENABLED, wx->flags);
        if (!wx->ring_feature[RING_F_VMDQ].limit)
 
        WX_FLAG_VMDQ_ENABLED,
        WX_FLAG_VLAN_PROMISC,
        WX_FLAG_SRIOV_ENABLED,
+       WX_FLAG_IRQ_VECTOR_SHARED,
        WX_FLAG_FDIR_CAPABLE,
        WX_FLAG_FDIR_HASH,
        WX_FLAG_FDIR_PERFECT,
 
         * for queue. But when num_vfs == 7, vector[1] is assigned to vf6.
         * Misc and queue should reuse interrupt vector[0].
         */
-       if (wx->num_vfs == 7)
+       if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags))
                err = request_irq(wx->msix_entry->vector,
                                  ngbe_misc_and_queue, 0, netdev->name, wx);
        else
 
 #define NGBE_PX_MISC_IC_TIMESYNC               BIT(11) /* time sync */
 
 #define NGBE_INTR_ALL                          0x1FF
-#define NGBE_INTR_MISC(A)                      BIT((A)->num_q_vectors)
+#define NGBE_INTR_MISC(A)                      BIT((A)->msix_entry->entry)
 
 #define NGBE_PHY_CONFIG(reg_offset)            (0x14000 + ((reg_offset) * 4))
 #define NGBE_CFG_LAN_SPEED                     0x14440