unsigned int pcmclk;
 };
 
+static int wm8990_volatile_register(struct snd_soc_codec *codec,
+                                   unsigned int reg)
+{
+       switch (reg) {
+       case WM8990_RESET:
+               return 1;
+       default:
+               return 0;
+       }
+}
+
 /*
  * wm8990 register cache.  Note that register 0 is not included in the
  * cache.
 static int wm8990_set_bias_level(struct snd_soc_codec *codec,
        enum snd_soc_bias_level level)
 {
+       int ret;
        u16 val;
 
        switch (level) {
 
        case SND_SOC_BIAS_STANDBY:
                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
+                       ret = snd_soc_cache_sync(codec);
+                       if (ret < 0) {
+                               dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
+                               return ret;
+                       }
+
                        /* Enable all output discharge bits */
                        snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
                                WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
 
 static int wm8990_resume(struct snd_soc_codec *codec)
 {
-       int i;
-       u8 data[2];
-       u16 *cache = codec->reg_cache;
-
-       /* Sync reg_cache with the hardware */
-       for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
-               if (i + 1 == WM8990_RESET)
-                       continue;
-               data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
-               data[1] = cache[i] & 0x00ff;
-               codec->hw_write(codec->control_data, data, 2);
-       }
-
        wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
        return 0;
 }
        .reg_cache_size = ARRAY_SIZE(wm8990_reg),
        .reg_word_size = sizeof(u16),
        .reg_cache_default = wm8990_reg,
+       .volatile_register = wm8990_volatile_register,
 };
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)