arm64: dts: qcom: sm8550: add iris DT node

Add DT entries for the sm8550 iris decoder.

Since the firmware is required to be signed, only enable
on Qualcomm development boards where the firmware is
publicly distributed.

Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250509-topic-sm8x50-upstream-iris-8550-dt-v4-1-22ced9179da3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 29bc1ddfc7b25f203c9f3b530610e45c44ae4fb2..9dfb248f9ab52b354453cf42c09d93bbee99214f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -945,6 +945,10 @@
        status = "okay";
 };
 
+&iris {
+       status = "okay";
+};
+
 &gpi_dma1 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 5648ab60ba4c4bfaf5baa289969898277ee57cef..fdcecd41297d6ebc81c5088472e4731ca0782fcb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -672,6 +672,10 @@
        };
 };
 
+&iris {
+       status = "okay";
+};
+
 &lpass_tlmm {
        spkr_1_sd_n_active: spkr-1-sd-n-active-state {
                pins = "gpio17";

diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 3a6cb279130489168f8d20a6e27808647debdb41..49438a7e77ceaab9506158855b6262206bca94ec 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -779,6 +779,10 @@
        status = "okay";
 };
 
+&iris {
+       status = "okay";
+};
+
 &gpi_dma1 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 82cabf777cd2c1dc87457aeede913873e7322ec2..71a7e3b57ecedd86d798e71b781451fe11f9c1ce 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3221,6 +3221,87 @@
                        };
                };
 
+               iris: video-codec@aa00000 {
+                       compatible = "qcom,sm8550-iris";
+
+                       reg = <0 0x0aa00000 0 0xf0000>;
+                       interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+                       power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+                                       <&videocc VIDEO_CC_MVS0_GDSC>,
+                                       <&rpmhpd RPMHPD_MXC>,
+                                       <&rpmhpd RPMHPD_MMCX>;
+                       power-domain-names = "venus",
+                                            "vcodec0",
+                                            "mxc",
+                                            "mmcx";
+                       operating-points-v2 = <&iris_opp_table>;
+
+                       clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+                                <&videocc VIDEO_CC_MVS0C_CLK>,
+                                <&videocc VIDEO_CC_MVS0_CLK>;
+                       clock-names = "iface",
+                                     "core",
+                                     "vcodec0_core";
+
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "cpu-cfg",
+                                            "video-mem";
+
+                       memory-region = <&video_mem>;
+
+                       resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
+                       reset-names = "bus";
+
+                       iommus = <&apps_smmu 0x1940 0>,
+                                <&apps_smmu 0x1947 0>;
+                       dma-coherent;
+
+                       /*
+                        * IRIS firmware is signed by vendors, only
+                        * enable in boards where the proper signed firmware
+                        * is available.
+                        */
+                       status = "disabled";
+
+                       iris_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-240000000 {
+                                       opp-hz = /bits/ 64 <240000000>;
+                                       required-opps = <&rpmhpd_opp_svs>,
+                                                       <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-338000000 {
+                                       opp-hz = /bits/ 64 <338000000>;
+                                       required-opps = <&rpmhpd_opp_svs>,
+                                                       <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-366000000 {
+                                       opp-hz = /bits/ 64 <366000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>,
+                                                       <&rpmhpd_opp_svs_l1>;
+                               };
+
+                               opp-444000000 {
+                                       opp-hz = /bits/ 64 <444000000>;
+                                       required-opps = <&rpmhpd_opp_nom>,
+                                                       <&rpmhpd_opp_nom>;
+                               };
+
+                               opp-533333334 {
+                                       opp-hz = /bits/ 64 <533333334>;
+                                       required-opps = <&rpmhpd_opp_turbo>,
+                                                       <&rpmhpd_opp_turbo>;
+                               };
+                       };
+               };
+
                videocc: clock-controller@aaf0000 {
                        compatible = "qcom,sm8550-videocc";
                        reg = <0 0x0aaf0000 0 0x10000>;