ARM: shmobile: r8a7790: add CAN clocks

The R-Car CAN controllers can derive the CAN bus clock not only from their
peripheral clock input (clkp1) but also from the other internal clock (clkp2)
and external clock fed on CAN_CLK pin.  Describe those clocks in the device
tree,  along with  the USB_EXTAL clock  from which clkp2 is derived.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 24de994443e18eae96cbd3c4bfeeb7dc94d24baf..e872854b4ba990e87961e4cbfd853c600496b948 100644 (file)
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -838,16 +838,34 @@
                        clock-output-names = "audio_clk_c";
                };
 
+               /* External USB clock - can be overridden by the board */
+               usb_extal_clk: usb_extal_clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <48000000>;
+                       clock-output-names = "usb_extal";
+               };
+
+               /* External CAN clock */
+               can_clk: can_clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       /* This value must be overridden by the board. */
+                       clock-frequency = <0>;
+                       clock-output-names = "can_clk";
+                       status = "disabled";
+               };
+
                /* Special CPG clocks */
                cpg_clocks: cpg_clocks@e6150000 {
                        compatible = "renesas,r8a7790-cpg-clocks",
                                     "renesas,rcar-gen2-cpg-clocks";
                        reg = <0 0xe6150000 0 0x1000>;
-                       clocks = <&extal_clk>;
+                       clocks = <&extal_clk &usb_extal_clk>;
                        #clock-cells = <1>;
                        clock-output-names = "main", "pll0", "pll1", "pll3",
                                             "lb", "qspi", "sdh", "sd0", "sd1",
-                                            "z";
+                                            "z", "rcan";
                };
 
                /* Variable factor clocks */

diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 91940271cf8347265849da044ba26a62228e5bd2..ffa8c11be68a25539f9e8c02b58dd61a0c647d88 100644 (file)
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -21,6 +21,7 @@
 #define R8A7790_CLK_SD0                        7
 #define R8A7790_CLK_SD1                        8
 #define R8A7790_CLK_Z                  9
+#define R8A7790_CLK_RCAN               10
 
 /* MSTP0 */
 #define R8A7790_CLK_MSIOF0             0