drm/i915/skl: Don't warn if reading back DPLL0 is disabled

We can operate with DPLL0 off with CDCLK backed by the 24Mhz reference
clock, and that's a supported configuration. Don't warn when notice
DPLL0 is off then.

We still have a separate warn at boot if cdclk is disabled (because we
don't currently try to handle the case (that shouldn't happen on SKL as
far as I know) where we boot with display not initialized.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9280e76505fce70baf93b219d3e7b66d8b0bb106..0a3456988c1278e913be3710539a7ea044dc6655 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6737,10 +6737,8 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
        uint32_t cdctl = I915_READ(CDCLK_CTL);
        uint32_t linkrate;
 
-       if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
-               WARN(1, "LCPLL1 not enabled\n");
+       if (!(lcpll1 & LCPLL_PLL_ENABLE))
                return 24000; /* 24MHz is the cd freq with NSSC ref */
-       }
 
        if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
                return 540000;