.require_force_probe = 1,
 };
 
+#define DG2_FEATURES \
+       XE_HP_FEATURES, \
+       XE_HPM_FEATURES, \
+       DGFX_FEATURES, \
+       .graphics.rel = 55, \
+       .media.rel = 55, \
+       PLATFORM(INTEL_DG2), \
+       .has_4tile = 1, \
+       .has_64k_pages = 1, \
+       .has_guc_deprivilege = 1, \
+       .platform_engine_mask = \
+               BIT(RCS0) | BIT(BCS0) | \
+               BIT(VECS0) | BIT(VECS1) | \
+               BIT(VCS0) | BIT(VCS2)
+
 __maybe_unused
 static const struct intel_device_info dg2_info = {
-       XE_HP_FEATURES,
-       XE_HPM_FEATURES,
+       DG2_FEATURES,
        XE_LPD_FEATURES,
-       DGFX_FEATURES,
-       .graphics.rel = 55,
-       .media.rel = 55,
-       .has_4tile = 1,
-       PLATFORM(INTEL_DG2),
-       .has_guc_deprivilege = 1,
-       .has_64k_pages = 1,
-       .platform_engine_mask =
-               BIT(RCS0) | BIT(BCS0) |
-               BIT(VECS0) | BIT(VECS1) |
-               BIT(VCS0) | BIT(VCS2),
-       .require_force_probe = 1,
        .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
                               BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+       .require_force_probe = 1,
+};
+
+__maybe_unused
+static const struct intel_device_info ats_m_info = {
+       DG2_FEATURES,
+       .display = { 0 },
+       .require_force_probe = 1,
 };
 
 #undef PLATFORM