drm/amd/powerplay: implement the interface for setting soft freq range

The APU soft freq range set by different way from DGPU, thus need implement
the function respectively base on each common SMU part.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index d9ef4ae4b8f65076ec6d94e7bd7e384b76089cda..7b995b0834ebd4f9c43639ab7bf78d2f0674dc0a 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -205,8 +205,7 @@ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t
 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
                            uint32_t min, uint32_t max)
 {
-       int ret = 0, clk_id = 0;
-       uint32_t param;
+       int ret = 0;
 
        if (min <= 0 && max <= 0)
                return -EINVAL;
@@ -214,27 +213,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
        if (!smu_clk_dpm_is_enabled(smu, clk_type))
                return 0;
 
-       clk_id = smu_clk_get_index(smu, clk_type);
-       if (clk_id < 0)
-               return clk_id;
-
-       if (max > 0) {
-               param = (uint32_t)((clk_id << 16) | (max & 0xffff));
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
-                                                 param);
-               if (ret)
-                       return ret;
-       }
-
-       if (min > 0) {
-               param = (uint32_t)((clk_id << 16) | (min & 0xffff));
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
-                                                 param);
-               if (ret)
-                       return ret;
-       }
-
-
+       ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
        return ret;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index f1b37896555199f2d8b2413c1b368904ef1c0c22..504d6487c3d2a35b9b342abebead12d04174fb84 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -548,6 +548,7 @@ struct smu_funcs
        int (*baco_reset)(struct smu_context *smu);
        int (*mode2_reset)(struct smu_context *smu);
        int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
+       int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
 };
 
 #define smu_init_microcode(smu) \
@@ -777,6 +778,8 @@ struct smu_funcs
 #define smu_get_dpm_uclk_limited(smu, clock, max) \
                ((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
 
+#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
+               ((smu)->funcs->set_soft_freq_limited_range ? (smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : -EINVAL)
 
 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
                                   uint16_t *size, uint8_t *frev, uint8_t *crev,

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index d50e0d07e6307ca28d3a7e548e388ab1e8ab21d5..c9e90d59a6b8f1a03c271a9bbdd4620d11e71bcf 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1763,6 +1763,35 @@ failed:
        return ret;
 }
 
+static int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+                           uint32_t min, uint32_t max)
+{
+       int ret = 0, clk_id = 0;
+       uint32_t param;
+
+       clk_id = smu_clk_get_index(smu, clk_type);
+       if (clk_id < 0)
+               return clk_id;
+
+       if (max > 0) {
+               param = (uint32_t)((clk_id << 16) | (max & 0xffff));
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
+                                                 param);
+               if (ret)
+                       return ret;
+       }
+
+       if (min > 0) {
+               param = (uint32_t)((clk_id << 16) | (min & 0xffff));
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
+                                                 param);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 static const struct smu_funcs smu_v11_0_funcs = {
        .init_microcode = smu_v11_0_init_microcode,
        .load_microcode = smu_v11_0_load_microcode,
@@ -1814,6 +1843,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
        .baco_set_state = smu_v11_0_baco_set_state,
        .baco_reset = smu_v11_0_baco_reset,
        .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
+       .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
 };
 
 void smu_v11_0_set_smu_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index d9d9473755578e7e0c6e5714657b6d8c0f6c16d8..d3563f0c44e9ac2f50f7201a2c46d2aefba7c72d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -383,6 +383,61 @@ failed:
 static int smu_v12_0_mode2_reset(struct smu_context *smu){
        return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2);
 }
+
+static int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
+                           uint32_t min, uint32_t max)
+{
+       int ret = 0;
+
+       if (max < min)
+               return -EINVAL;
+
+       switch (clk_type) {
+       case SMU_GFXCLK:
+       case SMU_SCLK:
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, min);
+               if (ret)
+                       return ret;
+
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, max);
+               if (ret)
+                       return ret;
+       break;
+       case SMU_FCLK:
+       case SMU_MCLK:
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min);
+               if (ret)
+                       return ret;
+
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max);
+               if (ret)
+                       return ret;
+       break;
+       case SMU_SOCCLK:
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min);
+               if (ret)
+                       return ret;
+
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max);
+               if (ret)
+                       return ret;
+       break;
+       case SMU_VCLK:
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinVcn, min);
+               if (ret)
+                       return ret;
+
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxVcn, max);
+               if (ret)
+                       return ret;
+       break;
+       default:
+               return -EINVAL;
+       }
+
+       return ret;
+}
+
 static const struct smu_funcs smu_v12_0_funcs = {
        .check_fw_status = smu_v12_0_check_fw_status,
        .check_fw_version = smu_v12_0_check_fw_version,
@@ -398,6 +453,7 @@ static const struct smu_funcs smu_v12_0_funcs = {
        .populate_smc_tables = smu_v12_0_populate_smc_tables,
        .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
        .mode2_reset = smu_v12_0_mode2_reset,
+       .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
 };
 
 void smu_v12_0_set_smu_funcs(struct smu_context *smu)