drm/amd/display: enable dsc_clk even if dsc_pg disabled

[why]
need to enable dsc_clk regardless dsc_pg

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 72dffb7a49f9e66db1acbced835f272c7edf4407..39e291a467e27b429cda05d5ad978dd02a257179 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1853,7 +1853,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
        if (dc->hwss.subvp_pipe_control_lock)
                dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
 
-       if (dc->debug.enable_double_buffered_dsc_pg_support)
+       if (dc->hwss.update_dsc_pg)
                dc->hwss.update_dsc_pg(dc, context, false);
 
        disable_dangling_plane(dc, context);
@@ -1960,7 +1960,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                dc->hwss.optimize_bandwidth(dc, context);
        }
 
-       if (dc->debug.enable_double_buffered_dsc_pg_support)
+       if (dc->hwss.update_dsc_pg)
                dc->hwss.update_dsc_pg(dc, context, true);
 
        if (dc->ctx->dce_version >= DCE_VERSION_MAX)
@@ -2207,7 +2207,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
 
                dc->hwss.optimize_bandwidth(dc, context);
 
-               if (dc->debug.enable_double_buffered_dsc_pg_support)
+               if (dc->hwss.update_dsc_pg)
                        dc->hwss.update_dsc_pg(dc, context, true);
        }
 
@@ -3565,7 +3565,7 @@ static void commit_planes_for_stream(struct dc *dc,
                if (get_seamless_boot_stream_count(context) == 0)
                        dc->hwss.prepare_bandwidth(dc, context);
 
-               if (dc->debug.enable_double_buffered_dsc_pg_support)
+               if (dc->hwss.update_dsc_pg)
                        dc->hwss.update_dsc_pg(dc, context, false);
 
                context_clock_trace(dc, context);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 76fd7a41bdbf7ff193947914fd208e5522e82f97..45b557d8e0890ba4219a03b0f934af63d66ee1aa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -77,6 +77,9 @@ void dcn32_dsc_pg_control(
        if (hws->ctx->dc->debug.disable_dsc_power_gate)
                return;
 
+       if (!hws->ctx->dc->debug.enable_double_buffered_dsc_pg_support)
+               return;
+
        REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
        if (org_ip_request_cntl == 0)
                REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 10ae1b3da75151fb552cbe9aca3437529fa03a93..6214866916c7ea5b9a42b916e0090fd768954a5c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -742,7 +742,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_mem_low_power = false,
        .enable_hpo_pg_support = false,
        //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
-       .enable_double_buffered_dsc_pg_support = false,
+       .enable_double_buffered_dsc_pg_support = true,
        .enable_dp_dig_pixel_rate_div_policy = 1,
        .disable_z10 = false,
        .ignore_pg = true,