gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return PHYS_SDRAM_1_SIZE;
+ return (0);
}
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return PHYS_SDRAM_1_SIZE;
+ return (0);
}
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE;
+ return (0);
}
bd->bi_dram[3].start = PHYS_SDRAM_4;
bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
- return (PHYS_SDRAM_1_SIZE +
- PHYS_SDRAM_2_SIZE +
- PHYS_SDRAM_3_SIZE +
- PHYS_SDRAM_4_SIZE );
+ return (0);
}
bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
- return ( 0
-#ifdef PHYS_SDRAM_1
- + PHYS_SDRAM_1_SIZE
-#endif
-#ifdef PHYS_SDRAM_2
- + PHYS_SDRAM_2_SIZE
-#endif
-#ifdef PHYS_SDRAM_3
- + PHYS_SDRAM_3_SIZE
-#endif
-#ifdef PHYS_SDRAM_4
- + PHYS_SDRAM_4_SIZE
-#endif
- );
+ return (0);
}
int i, j;
ulong size = 0;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
- {
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
flash_info[i].flash_id =
(INTEL_MANUFACT & FLASH_VENDMASK) |
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x0C000100;
- return 1;
+ return 0;
}
int dram_init (void)
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return PHYS_SDRAM_1_SIZE;
+
+ return 0;
}
dram_init, /* configure available RAM banks */
display_dram_config,
+ NULL,
};
void start_armboot (void)
/* Pointer is writable since we allocated a register for it */
gd = &gd_data;
- gd->bd = &bd_data;
-
- /* initialize internal data strucuture */
memset (gd, 0, sizeof (gd_t));
+ gd->bd = &bd_data;
memset (gd->bd, 0, sizeof (bd_t));
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {